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ISSUE 38 | Q3 2024
The impact of optical connectivity on LLM | p8 UNLOCKING AI’S POTENTIAL:
µ LED BASED INTERCONNECTS: UNLEASHING THE POTENTIAL OF HPC & AI | p10
EPIC CEO INTERVIEW: David Creasey | p30
AI TEST & MEASUREMENT: Companies rise to the AI challenge | p21
CLOUD DRIVES CONVERGED ARCHITECTURE NEW UCIe SPEC NOKIA FIRST WITH BEAD PRODUCTS
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CONTENTS
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Industry News
Linear Pluggable Optics Peter Dykes
ECOC LOOKS TO THE FUTURE
8 Unlocking AI’s Potential Christian Uricarriet 10 μLED Based Interconnects: Dr Jess Brown 12 CMIS John Williamson 16 SDANs Filip De Greve 18 The Rise of Coherent Pluggables Fady Masoud 21 AI Test & Measurement Tony Savvas 24 Debunking Fibre Cleaning Myths Liam Taylor 26 High-Density Infrastructure Thomas Ritz & Andreas Rü sseler 30 EPIC CEO Interview David Creasey 32 ECOC 2024 Preview 33 ECOC 2024 Market Focus 35 ECOC 2024 Industry Awards 36 Connected Britain Preview 40 Product Focus
Welcome to the Autumn 2024 edition of Optical Connections. ECOC is upon us once again offering a wide range of new products and presentations ranging from FTTx rollout to photonics. Most of all, it provides a glimpse of the future of this exciting industry. In this issue, we aim to echo some of the developments taking the industry going forward, with thought leadership features by industry experts and leading journalists in the field. Ultra high-speed chip-to-chip optical communication is becoming a critical area of development to meet the demands of AI and ML, and in this issue, we look at two different approaches to these challenges by Intel’s Christian Urricariet and Avicena’s Dr Jess Brown . Pluggables are also a rapidly developing sector, and we talk to Laurent Hendrichs and Pete Del Vecchio at Broadcom, about the rise of Linear Pluggable Optic transceivers. In addition, Infinera’s Fady Masoud takes a deep dive into the rise of intelligent pluggables. However, the onset on AI and ML means greater demands on physical space in access points and data centres, and R&M’s Thomas Ritz and Andreas Rü sseler look at high-density infrastructure as a possible solution. In addition, long-time telecoms writer Antony Savvas takes a look at how companies are leveraging AI to solve new test and measurement challenges, and veteran journalist John Williamson talks to Ian Alderdice and Gary Nicholl at the OIF, about the development of the Common Management Interface Specification (CMIS), so crucial for commonality in managing pluggable modules. Another challenge facing the industry is the speed with which fibre can be rolled out to homes and premises across the world, and Nokia’s Filip D Greve explains how Software Defined Access Networks (SDAN) can meet this and many other challenges. Of course, with the literally millions of connections and splices involved in next-gen fibre networks, cleanliness is of vital importance and MicroCare’s Liam Taylor debunks some of the most common fibre optic end face cleaning myths, and provides insights into best practices. All this, along with the usual features is a great curtain-raiser for what will be on display at ECOC 2024. Have a great show!
Peter Dykes Contributing Editor
READ ONLINE/SUBSCRIBE: www.opticalconnectionsnews.com FOLLOW US @opconsnews EDITORIAL : editor@opticalconnectionsnews.com ADVERTISING: sales@opticalconnectionsnews.com DESIGN: Antonio Manuel
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ISSUE 38 | Q3 2024
INDUSTRY NEWS
Cloud operators drive adoption of converged architecture
Cloud Operator Datacentre Interconnect (DCI) is propelling high volume adoption of coherent pluggable optics, according to the latest Active Insight report, IP-over-DWDM Pluggables Forecast, from research firm Cignal AI. The analyst says IP-over-DWDM, which is the practice of using coherent optics directly within routers and switches, has transformed how Cloud Operators connect their data centres over short distances. The standardization, development, and maturation of 400G pluggable coherent optics (400ZR) has fortuitously coincided with the ongoing AI spending boom, with
volumes increasing faster than any previous DWDM technology. The report also finds that Cloud Operators, predominantly the big four hyperscalers, will continue to be the driving force behind the technology and volume of pluggable coherent transceivers, and that 400G purchases by Cloud Operators will peak in 2026 once the adoption of 800G and 1600G begins. In addition, it finds that the performance gap between embedded and pluggable optics will further shrink with 1600G, making IP-over- DWDM even more attractive from a network design perspective. However, the
rate of adoption for IP- over-DWDM will be slow and steady. Despite the operational hurdles, the technology’s space, power, and cost benefits will justify the change in architecture for many operators. “The market for router- hosted pluggables is already sizeable, but it will continue to further grow as operational issues are solved and new generations of optics evolve,” said Kyle Hollasch, lead analyst at Cignal AI. “The uptake of IP-over-DWDM will vary significantly between Cloud Operators and traditional Service Providers, as will the preferences for the speed and module type.” IP-over DWDM Pluggables
Forecast is part of Cignal AI’s Active Insight research service and leverages data from the Optical Components and Transport Hardware reports. This Active Insight report provides forecasts for IP-over-DWDM module deployment by operator type (Cloud, Traditional Service Provider, Enterprise and Government) and coherent module speed (400G, 800G, 1600G). Active Insight reports provide real-time reporting on important developments in the optical market, including detailed analysis of key product trends, show reports, summaries of quarterly earnings calls, and vendor reports.
UCIe Consortium Releases 2.0 Specification
Nokia first to self-certify fibre products for use in BEAD
The Universal Chiplet Interconnect Express™ (UCIe™) consortium has announced the release of its 2.0 Specification. The UCIe 2.0 Specification adds support for a standardised system architecture for manageability and holistically addresses the design challenges for testability, manageability, and debug (DFx) for the SIP lifecycle across multiple chiplets – from sort to management in the field. The introduction of optional manageability features and a UCIe DFx Architecture (UDA), which includes a management fabric within each chiplet for testing, telemetry, and debug functions, allows vendor agnostic chiplet interoperability across a flexible and a unified approach to SIP management and DFx operations. The UCIe 2.0 Specification includes holistic support for manageability, debug, and testing for any System-in- Package (SiP) construction
Nokia says it has become the first technology vendor to self-certify its fibre products manufactured in the U.S., ensuring each meets the requirements outlined in the recently announced BABA compliance and self-certification guidelines for the BEAD program. BEAD Applicants can now obtain a Certification Letter from Nokia to prove BABA compliance. The products include Nokia’s FX and MF OLT modular product lines, the SF-8M sealed OLT, and the XS-220X-A ONT. Operators and infrastructure players seeking
with multiple chiplets; improved system-level
Manufacturers that complete the self-certification process are added to a list managed by the Department of Commerce. Focused on reducing the number of fraudulent claims of BABA compliance, the list requires manufacturers to have an
solutions with manageability defined as part of the chiplet stack; and fully backward compatibility with UCIe 1.1 and UCIe 1.0. Additionally, the 2.0 Specification supports 3D packaging – offering higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures. UCIe-3D is optimised for hybrid bonding with a bump pitch functional for bump pitches as big as 10-25 microns to as small as 1 micron or less to provide flexibility and scalability. Another feature is optimised package designs for interoperability and compliance testing. The goal of compliance testing is to validate the main-band supported features of a Device Under Test (DUT) against a known- good reference UCIe implementation. UCIe 2.0 establishes an initial framework for physical, adapter, and protocol compliance testing.
officer of the company certify – under fine or imprisonment – that its
products are Buy America- compliant. Manufacturers must also be able to provide a BABA certification letter to subgrantees for audit purposes Sandy Motley, President of Fixed Networks at Nokia, said, “We are excited to announce yet another milestone in our BEAD journey. As a certified vendor, we can now provide BEAD applicants with a certification letter that’s become essential for applications and BABA reporting requirements. It also provides the confidence and assurance several need to submit product orders today without fear of being out of compliance.
to participate in BEAD and the US$42.45bn of
available funding will need to ensure – under federal penalty – that certain fibre broadband equipment used in their network buildouts are manufactured in the U.S. To help, the NTIA created a self-certification and compliance framework for manufacturers, allowing each to show its products meet these requirements.
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ISSUE 38 | Q3 2024
Q&A BROADCOM LINEAR PLUGGABLE OPTICS
LINEAR PLUGGABLE OPTICS:
A REVOLUTION IN THE MAKING? Linear Pluggable Optics (LPO)s is revolutionising the way data centres, telecommunication networks, and enterprise IT infrastructures manage and transmit data. This cutting-edge technology leverages modular optical transceivers, which have a number of advantages including lower power consumption and greater reliability than those currently in use. Optical Connections editor Peter Dykes spoke with Laurent Hendrichs , senior product line manager of high-speed Ethernet adapters and Pete Del Vecchio , Data Centre Switch Product Line Manager at Broadcom, to find out more about this emerging technology.
What factors are driving the development of LPO?
What are the main technical differences between LPO and pluggables in common use today
What sort of throughput speeds can LPOs achieve currently and in the future? 800G and 400G LPO transceivers are available today. The current target of OIF and the LPO MSA is
PD
PD
PD
(e.g. ZR, ZR+ etc)?
It depends on who you ask. Hyperscalers view it as a way to improve AI compute density by
LH
LH
The essential difference is the elimination of the DSP from the optical module made possible by
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reducing the power consumed in the network, thereby leaving more power available for GPUs. Network reliability is a second driver. Simpler modules with fewer active components are inherently more reliable than conventional designs. However, more importantly, the lower power of LPO transceivers enables them to run at lower temperatures, which considerably improves reliability. Broadcom estimates a 3x improvement in MTTF (Mean time to failure) for LPO vs conventional optics. Server vendors like LPOs for their low power consumption. This is especially important for network adapters deployed in hot-aisle configurations, where the optics are cooled by hot exhaust air coming from inside the server. In such configurations, it is particularly challenging to cool conventional optical transceivers. LPO transceivers, in contrast, require much less cooling airflow due to their lower power. Broadcom estimates that LPOs offer up to 40-60% power reduction over conventional equivalents. Finally, cost-sensitive users appreciate the lower cost of LPOs made possible by the elimination of the DSP inside the module.
100G serial links. Work is already in progress, however, for 200G serial.
the advanced capabilities of the SerDes in the latest generation of Ethernet NIC and switch ASICs. As an example, Broadcom has included in their recent SerDes design features that were previously only found in optical DSPs. With LPO transceivers, equalisation or reconditioning of the signal is therefore done inside the NIC or switch ASIC.
Where does LPO fit into the future marketplace for pluggables?
PD
We expect to see multiple technologies coexist in the market. There will be use cases
LH
for LPO, Linear Receive Optics (LRO), Co-packaged optics (CPO), and retimed optics. Adoption of a particular technology will result from a trade-off between performance and the imperative need to reduce connectivity power as SerDes speeds increase and AI servers pack ever more compute density. Module vendors such as Eoptolink are already offering commercially available LPO transceivers. A selection of LPO transceivers will feature on the module compatibility list of server vendors. Hyperscalers who typically prefer to use cables will likely adopt Active Optical Cables (AOC), in which one or both transceivers will use the LPO technology.
Is it possible to mix LPO and existing pluggables?
PD
Yes. Broadcom and multiple other equipment vendors have demonstrated the feasibility of
LH
deploying LPO transceivers on one side of the link and conventional transceivers on the other side. This is the focus of Optical Internetworking Forum (OIF). An OIF-compliant LPO module will be fully compatible with the existing optics ecosystem. By contrast, the LPO MSA focuses on LPO-to-LPO links, allowing for lower power, lower cost, and better end-to- end link performance by removing the constraint of compatibility with retimed optics.
Will DSPs still have a role in optical transmission if LPO becomes widely used?
PD
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Q&A BROADCOM LINEAR PLUGGABLE OPTICS
Yes. DSPs will continue to offer more advanced signal processing capabilities than those available in
What we see is a spectrum of connectivity technologies, with different power, performance and
only go so far, as their length is limited to 2 meters in the IEEE standard. However, the latest generation of Broadcom Ethernet ASICs supports passive cables up to 5 meters. Beyond that, optical cables are required. LPOs represent a mid-way technology, as they are not as good as passive copper cables, but significantly better than conventional optics in terms of power, reliability and cost. Given their sizable benefits and absence of any major shortcomings, we expect to see widespread adoption of LPOs over the coming years.
LH
LH
Switch and NIC ASICs. Cables exceeding a certain length will continue to require DSPs to achieve an acceptable Bit Error Rate.
cost merits. The LPO technology fills a gap between passive copper cables and retimed optics. Other technologies such as co-packaged optics (CPO) offer even lower power and cost than LPO. Power, reliability and cost are three major technical challenges impacting the deployment of AI networks. Passive copper cables offer by far the best technology over short distances, as they draw almost no power, are several orders of magnitude more reliable than active cables and are unbeatable from a cost point of view. But passive copper cables
How is the MSA group progressing LPO and what is the future roadmap?
PD
PDV The LPO MSA work is under NDA and only limited information is made available to the public. The MSA focuses on optimising LPO-LPO links. Free from the compatibility constraints with non-LPO transceivers, the MSA’s aim is to offer the lowest cost and power for a given performance level. Future work in the MSA will include standards for LRO. (Linear Receive Optics = half-retimed optics). Is Broadcom working on a particular aspect of the MSA? Broadcom is a founder and active contributor working on all aspects of the MSA. Peter Del Vecchio, who manages the Tomahawk product line, is co-chair. Karl Muth, a senior engineer in Broadcom’s switch business units, is editor for the specification.
Thank you.
PD
Do you think LPO is a small step or a quantum leap in pluggable transceiver technology?
Laurent Hendrichs Senior Product Line Manager of high-speed Ethernet adapters
Pete Del Vecchio Data Centre Switch Product Line Manager at Broadcom
PD
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ISSUE 38 | Q3 2024
CHRISTIAN URRICARIET OPTICAL CONNECTIVITY
THE IMPACT OF OPTICAL CONNECTIVITY ON LARGE LANGUAGE MODELS Christian Urricariet , Senior Director of Product Marketing for Integrated Photonics Solutions at Intel, looks at how Generative AI and large language models are driving unprecedented requirements on AI infrastructure and its ability to keep up with model sizes. New interconnect technologies are necessary to enable massive scaling of bandwidth as well as clusters and fabric. Connectivity in the form of a new class of optical interfaces offers a solution that provides high-bandwidth, low-latency GPU links at a cost and power efficiency that is scalable. As an example of this emerging segment, Intel’s Optical Compute Interconnect (OCI) chiplet recently demonstrated shows us a glimpse of the future – Compact, power-efficient co-packaged optical I/O with performance to enable scaling of AI resources. UNLOCKING AI’S POTENTIAL:
I n the field of artificial intelligence, the development of large language models (LLMs) has been a game- changer, enabling a range of complex applications that can understand and generate human- like text. However, the computational demands of these models, which can have tens of billions of parameters or more, are immense. Training and running such models require distributing tasks across many GPUs, which often leads to inefficient utilization due to the memory-intensive nature of the workloads. To address this, larger batch sizes are used, but this solution introduces latency and requires even more GPUs to maintain parallel processing efficiency. The traditional approach of simply scaling up the number of GPUs is not without challenges. High-density GPU configurations consume significant power and necessitate specialized cooling solutions and infrastructure. Even less dense systems are limited by the performance constraints of copper interconnects and require additional
switching levels for larger deployments. Optical connectivity has emerged as a promising solution to these limitations. It provides high-bandwidth, low-latency connections between GPUs, which not only lowers power consumption but also facilitates better cooling and more efficient data transfer. This advancement is poised to accelerate the training and inference of LLMs by enhancing latency, throughput, and GPU utilization. Moreover, it allows for more flexible GPU placement, which is essential for reducing power and thermal loads, thereby improving the total cost of ownership. Kernel parallelism, which distributes computations across multiple GPUs, greatly benefits from optical connectivity. The reduced latency in communication between GPUs leads to improved performance and efficiency, making it possible to train larger and more complex AI models. Despite the potential of optical connectivity, the current generation of pluggable optical transceiver modules used in data centers and early
AI clusters cannot meet the scaling requirements for emerging AI workloads due to their size, cost, and power consumption. New integrated optical connectivity solutions co-packaged with GPUs are required, which can provide the higher bandwidth density, energy efficiency, low latency, lower cost, and extended reach needed for scaling AI infrastructure. These so-called Optical Compute Interconnect (OCI) applications can be enabled by aggressive integration along three different vectors. Firstly, increased integration at the PIC level, including on-chip DWDM lasers and SOAs to efficiently support scaling through increases in the number of wavelengths, larger number of fibers, and optionally on-chip laser sparing. The use of silicon photonics process technology for the PIC leverages the existing high-yielding and scalable manufacturing and testing infrastructure from CMOS processes, and the hybrid integration of the laser on chip allows the delivery of fully tested, Known-Good-Die (KGD), for
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CHRISTIAN URRICARIET OPTICAL CONNECTIVITY
Intel OCI Chiplet
maximum yield. Integrating the laser and SOA at wafer-scale results in minimal coupling losses for improved performance, lower cost due to the lack of laser back-end, and greatly improved reliability compared to discrete lasers. An alternative approach to on-chip integrated lasers is to use an External Laser Source (ELS) where the lasers are independently packaged and connected to the PIC via multiple optical connectors and fiber assembly. This adds significant cost and complexity to the design, greatly increasing the transmitter output power needed, and typically requiring the use of specialized Polarization Maintaining Fiber (PMF). Although this approach may provide some heat management benefits in some implementations, we believe these will be more than offset by its disadvantages as well as by the improvements in fully integrated device performance and manufacturing process described later in this article. The second vector is the heterogeneous integration of the PIC with the EIC, using advanced packaging to create the die stack or chiplet. Heterogeneous integration decouples improvements implemented on the EIC from the PIC, and it allows leveraging Moore’s Law to use the best CMOS IC node suited for each application. Thirdly, tighter integration with the host CPU/GPU through system- level packaging co-designs that maximize yield by using known good components, which are themselves fully integrated and tested. The transition from direct attachment of a fiber pigtail to a pluggable, reusable optical connector will result in reflow- compatible assemblies and simplify system-level fiber management and handling. It enables the realization of the photonics-chiplet equivalent of the CMOS KGD concept: A complete optical I/O subassembly including laser sources and optical termination, which is tested and characterized before it flows downstream for integration with
high-value GPU packages. Intel Corporation has made a significant breakthrough in this space with the demonstration of a fully integrated OCI chiplet at OFC 2024. This first chiplet was shown co- packaged with an Intel CPU, running an error-free PCIe Gen5 link over fiber. It is designed to support 64 channels of 32 Gbps data transmission in each direction (4Tbps aggregate) over fiber optics up to 100 meters. The current chiplet’s energy efficiency of 5pJ/ bit is significantly lower than current pluggable optical transceiver modules. Looking ahead, Intel has an aggressive development roadmap to scale the performance of future OCI chiplets, with the potential to reach 32 Tbps bandwidth and a shoreline density greater than 1.5Tbps/mm in the next few years by increasing line rate per channel, wavelengths per fiber, number of fibers, and polarization modes. The technical challenges that need to be solved include thermal management, advanced package design, and power delivery. Intel is addressing these challenges by considering standardized die-to-die (D2D) electrical interfaces that facilitate integration with a variety of hosts. The company is also working on improving the performance and reducing the device size (which directly impacts the economics significantly) and power consumption in future OCI chiplets through more advanced designs and the implementation of next-generation manufacturing process nodes for both the PIC and the EIC. Intel’s leadership in silicon photonics is well established, with over 25 years of research and development leading to the shipping of many millions of silicon photonics-based connectivity products into the hyperscale cloud data centers with proven high reliability (<0.1 laser FIT). Our mature platform has demonstrated the ability to increase functionality on-chip through increased component integration, from less than 100 devices/PIC in 2016 to about 2,000
devices/PIC today. The company’s integration approach of using hybrid laser-on-wafer technology results in higher reliability and lower costs, setting Intel apart from the capabilities of most competitors. The path to fully implementing integrated optical connectivity solutions in AI clusters is not without challenges. Reducing the cost of optical components and efficiently integrating these solutions into existing data center infrastructure requires ongoing investment and effort. However, the current technology path promises to revolutionize the training and inference of LLMs by overcoming the limitations of current hardware and infrastructure, leading to unprecedented advancements in AI.
Christian Urricariet is Senior Director of Product Marketing for Integrated Photonics Solutions at Intel. For more information, visit www.intel.com/siliconphotonics
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ISSUE 38 | Q3 2024
DR JESS BROWN µ LED BASED INTERCONNECTS
MULTI-TERABIT µLED BASED INTERCONNECTS: UNLEASHING THE POTENTIAL OF HPC AND AI. The demand for processing power in HPC (High Performance Computing), AI (Artificial Intelligence) and ML (Machine Learning) is increasing at an unprecedented rate and although Moore’s law isn’t happening anymore, by its strictest definition, it is still delivering steady improvements in processor performance, albeit at a slower pace. However, the same improvements are not being seen for the chip-to-chip and chip- to-memory interconnect technology, where there is an ever-widening gap between the needs and the reality, writes Dr Jess Brown , Business Development, Avicena.
T he growth in Large (HBM) stacks, as shown in Figure 1. In fact, over the last 5 years LLM parameter count has grown by several orders of magnitude, whereas HBM memory bandwidth has only grown by one order of magnitude. Electrical interconnects have fundamental limits in terms of reach, size and power efficiency, especially at higher data rates, which is causing this disparity. Therefore, there is a need for low power, compact, short-reach, fast link technologies at a reasonable price point. This article delves into the revolutionary realm of optical links based on GaN µLEDs, offering a transformative approach to chip-to-chip interconnects that promise unparalleled levels of ultra- low power consumption, exceptional bandwidth density, and minimal latency, which is in stark contrast to existing SerDes-based solutions. Language Models (LLMs) has completely outpaced the increase in memory bandwidth for in-package high-bandwidth memory INTERCONNECTS: THE OPTIONS There are two types of interconnect base technologies available: electrical and optical. The diagram below (Figure 2) shows a Figure-of-Merit (FoM) for these two types of technology in different configurations. The FoM plots the product of bandwidth density and energy efficiency against link reach, from 0.1mm to 1,000m. For short reach communications (<10cm) electrical links still currently offer the best performance, whereas for long distance communications (>10m), conventional optical technologies offer the best
Figure 1: LLM Parameter Count Outpacing Memory Bandwidth.
lane, which adds a significant overhead in terms of power. Therefore, there is currently a gap between electrical and existing optical solutions, since these technologies cannot provide an optimum solution for on-board data transfer, typically in the 1cm to 10m distance, which is the range for most chip-to-chip interconnects. Avicena’s technology can fill this void and provide advantages with an optical µLED based interconnect chiplet, offering ultra-fast, low-power interconnects that bridge the gap between internal processing performance and chip-to-chip communications, for interconnects that reach up to 10m. TO SERDES OR NOT TO SERDES Distributed data processing needs high speed data transfer between ICs, whether that is between the processors, between the processors and memory, or both.
performance, but for the middle range of 1cm to 10m neither offers optimum performance. Existing multi-mode Vertical-Cavity Surface-Emitting Laser (VCSEL) based links, although well suited for distances up to 100m, are not ideal for shorter optical interconnects, primarily because high-density processors run at elevated temperatures and VCSELs have a limited tolerance for high temperature operation. Silicon Photonics (SiPh) represent another optical link technology under development and evaluation. However, these were originally developed for medium to long-haul applications, which translates to SiPh interconnects having poor efficiency performance (>5pJ/bit) for short reach interconnects. Moreover, both VCSEL and SiPh based links typically use Serialisers/De-serialisers (SerDes), discussed in the next section, to achieve the high link bandwidth of > 100Gbps per
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DR JESS BROWN µ LED BASED INTERCONNECTS
individual µLED link or provide a simple muxing/demuxing function to keep latency and energy consumption to a minimum. A prime candidate for the electrical interface is the Universal Chiplet Interface Express (UCIe) which is gaining broad industry support, but other protocols like BoW or the emerging UALink are possible as well. Table 1 compares the advantages and disadvantages of parallel versus SerDes as well as the option of Avicena’s µLED optical solution and it can be seen here that Avicena’s LightBundle solution offers the best solution for chip-to-chip communications and interconnects.
Figure 2: The merit for bandwidth density and energy efficiency vs reach.
bundle to the matching array of PDs on the corresponding receiver transceiver ASIC and vice versa. A typical LightBundle link has a few hundred channels each operating at a few Gbps, providing aggregate throughputs of > 1Tbps per link. The modest per-channel speeds are well- matched to typical IC clock speeds and obviate the need for SerDes and enable the most efficient optical links at <1pJ/bit. GaN
Parallel and serial communications are the two options to transfer data between these chips. Parallel data transfer requires multiple connections between ICs, whereas serial data transfer only needs one pair of connections. On-chip communications is typically completed in a parallel format, so to enable serial interconnects a Serialiser-Deserialiser (SerDes) function block providing parallel to serial and serial-to-parallel conversion is required to enable serial communication between the two blocks. The transmitter section is a parallel to serial converter and the receiver section is a serial to parallel converter and most devices offer full-duplex operation, i.e. data in both directions at the same time. The reason for SerDes is to reduce the number of data paths needed to transmit data (and the associated number of connecting pins or wires) while achieving high link bandwidth. It additionally addresses other issues that come with transmitting parallel data electrically, such as susceptibility to electromagnetic interference and the likelihood of clock timing skew. A SerDes chip might also include an encoder, clock multiplier unit, physical coding sub-block, clock and data recovery unit, input and output staging areas, Forward Error Correction (FEC) blocks and other components. For long distance optical links there are clear advantages for using SerDes based interconnects because they minimise the number of costly, laser- based transmitters. However, when connecting ICs over distances of up to a few meters, there are clear advantages of using parallel links because ICs feature wide and relatively slow buses with clock speeds of a few Gbps internally. Avicena have developed an optical solution, using µLEDs, that overcome the disadvantages of SerDes, but still employ optical technology to gain all the associated benefits. Removing the need for SerDes, Avicena’s LightBundle TM consists of an array of GaN µLEDs and Si PDs bonded to a transceiver ASIC. The µLEDs are connected via a fibre
Table 1 Comparison of Parallel, Serial and µLED Optical Interconnect Solutions.
CONCLUSION Due to the limitations of traditional SerDes based optical interconnects the HPC, AI and IC industry is constantly evaluating innovative solutions to enable high bandwidth density, high energy efficiency and low latency interconnects for short to intermediate reach of up to a few meters. µLED technology, renowned for its application in high-resolution displays and lighting systems, has demonstrated the potential to redefine the landscape of data communication at the chip level. By combining the intrinsic advantages of light as a medium for data transmission with the 2D layout of LED arrays, µLED based optical links present a
µLEDs are already used in free-space Visible Light Communications (VLC), but at limited data rates. Avicena have managed to develop µLEDs that can operate at data rates of over 10Gbps. With this patented technology it has been demonstrated that not only can these µLEDs be modulated at high data rates, but they can also achieve bandwidth densities of > 2Tbps/mm with a power efficiency of < 1pJ/bit. The LightBundle transceiver chiplet can be either co-packaged with the processor using a silicon interposer or an organic substrate or it can be placed on the board and connected to the processor IC package via PCB traces. The only thing that changes in the different applications is the electrical interface between the LightBundle IC and the processor IC. Fundamentally, any electrical interface can be supported by the LightBundle interconnect. The LightBundle transceiver ASIC will convert the electrical data format to match the optical µLED transmission format. Parallel electrical interfaces are best suited to work in combination with the parallel optical µLED array interface of the LightBundle chiplet since no power hungry SerDes will be needed. The IC will either match the electrical lane rate to the data rate of each
ground-breaking avenue for achieving previously unattainable levels of performance in
interconnect architectures.
Dr Jess Brown, Business Development, Avicena.
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ISSUE 38 | Q3 2024
JOHN WILLIAMSON CMIS
OIF: CMIS OVERVIEW AND ROADMAP Work by OIF on expanding the already substantial remit and utility of the Common Management Interface Specification (CMIS) is gathering speed. Optical Connections’ John Williamson
interviewed OIF to discuss the origins, necessity and future plans of this crucial optical interface standardisation effort. Ian Alderdice , OIF Physical and Link Layer Working Group – Management Co- Vice Chair and Ciena and Gary Nicholl , OIF Physical and Link Layer Working Group – Management Co-Vice Chair and Cisco kindly provided detailed, joint responses to the questions.
C
M
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CM
How, when and where did the CMIS originate?
What does the CMIS aim to facilitate?
In addition, OIF uses white papers, industry conferences and webinars to discuss CMIS-based topics. Leaders from OIF are regulars on conference panels, discussing various management topics. The team has published, and will continue to publish white papers on management challenges, solutions and visions for the future. OIF is hosting a series of webinar tutorials that provide technical education on various CMIS topics, with each webinar drawing hundreds of participants. Details of OIF webinars are available from the organisation’s website.
JW
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OIF CMIS originated in the Quad Small Form Factor Pluggable- Double Density Multi-Source Agreement (QSFP-DD MSA) advisor’s group, led by a small group of management experts to harmonise the management interface for the new QSFP-DD and Octal Small Form Factor Pluggable (OSFP) module form factors. The original group published CMIS 3.0, the first public version of CMIS, in 2018. They updated and maintained the CMIS specification up to and including CMIS 5.1 when ownership transitioned to OIF.
CMIS provides the required tools to manage optical modules in a common way. Common
OIF
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interfaces reduce development effort and integration time, leading to faster market introduction of new technologies. The team that maintains and updates CMIS draws on industry experts from module vendors, host vendors and service providers, leading to a specification that addresses the needs of all layers of the optical module ecosystem.
Why do we need the CMIS?
JW
In this context, how does the OIF operate/work to advance the CMIS standard?
JW
Why did the OIF adopt the CMIS, and what OIF initiatives does it slot into? The QSFP-DD MSA initiated the CMIS effort to address an industry need for commonality in
JW
OIF A single common management interface reduces development effort for host and module vendors, leading to faster technology introduction. Common code bases allow for faster module integration and higher software quality. Reduced module integration times benefit service providers by reducing operational expenses and accelerating end-product time-to-market.
OIF The OIF management track advances CMIS through regular updates to the standard that are driven by member companies. Member companies can submit project start contributions for major work items or technical contributions for small/medium work items. These contributions are reviewed by the management track team during OIF quarterly meetings for project starts and weekly meetings for technical contributions. If the team accepts a work item, the item will ultimately be included in a new draft of the CMIS specification which then follows the standard OIF balloting and comment resolution process.
OIF
managing pluggable modules, and it was broadly and successfully adopted across the industry. Adopting CMIS to build on and extend the specification was an ideal expansion of OIF’s work. OIF has always strived to provide useful interface standards that further optical module interoperability. In the past, these standards have primarily been focussed on optical and electrical interfaces, but the management interface is also required to build inter-operable optical modules.
Is the CMIS application space expanding?
JW
OIF Yes, CMIS is continually evolving to add new applications and functionality. Some changes are more incremental like adding support for
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JOHN WILLIAMSON CMIS
Common interfaces reduce development effort and integration time, leading to faster market introduction of new technologies.
What are the challenges to further adoption?
Fibre Channel and coherent optics. Other additions are much larger like the addition of link training functionality and support for co-packaged optics.
continue to increase in speed. Co- packaging is a new area for CMIS and will likely evolve in the coming years. Support for Linear-drive Pluggable Optics (LPO) and Retimed Tx Linear Rx (RTLR) optics are being added. Work on transitioning the industry to higher speed management interfaces like I3C and Ethernet is on-going. Readers may be interested in two OIF CMIS-related White Papers announced in June 2024. One is a CMIS White Paper on Management of Smart Optical Modules and the other deals with CMIS-Based Out-of-Band Messaging for Link Training. OIF white papers are not standards but are intended to identify industry challenges, understand requirements and stimulate discussion on potential solutions. The outcome of a white paper may or may not lead to an OIF project.
JW
The transition to new interfaces and concepts will be the biggest challenge for CMIS. Such as
OIF
What are a couple of important OIF CMIS achievements/ milestones so far? Publishing the first version of CMIS under OIF was an important milestone. CMIS 5.2 was released
JW
convincing host and module vendors to add new interfaces like I3C and Ethernet to host sockets and modules across the industry and changing to a message- based solution. Finding a transition plan that supports the existing management interface and allows the industry to move towards future management interfaces will be a challenge.
OIF
quickly, showing that OIF’s process can meet the timing needs of the industry. CMIS 5.2 provided Fibre Channel enhancements that were important to that industry segment and showed that the OIF management track was servicing all types of optical modules. The CMIS interop demos and CMIS webinars have both been successful in sharing technical information on how CMIS works with the broader industry. Through these events, OIF has raised awareness of what CMIS is and how it works.
What work is currently underway on the spec and what is the future roadmap? CMIS 5.3 is in the final stages of being published and work is beginning to define content for
JW
OIF
the next version. Coherent-CMIS (C-CMIS) is about to start a new version adding support for 800G/1600G. Link training will be an active area in the coming years as electrical interfaces
How widely is CMIS being adopted and what plans are in place to further adoption? CMIS has been chosen as the management interface for nearly all new optical module projects in
JW
OIF
the past few years. CMIS is the management interface for the QSFP-DD and OSFP module form factors, which together represent the majority of the optical module market for 400Gbps and 800Gbps data rates. This is due to the strong technical underpinnings of the specification and the willingness of the OIF team to evolve the specifications to meet the needs of new technologies. Looking forward, OIF has been active
in preparing for the management needs of future optical modules.
Current contributions and projects are considering the addition of higher- speed management interfaces, including Improved Inter-Integrated Circuit (I3C) and Gigabit Ethernet. In addition, there have been multiple contributions and discussions about moving from a register-based interface to an object- based/message-based interface.
Ian Alderdice OIF Physical and Link Layer Working Group – Management Co-Vice Chair and Ciena
Gary Nicholl OIF Physical and Link Layer Working Group – Management Co-Vice Chair and Cisco
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FILIP DE GREVE SDAN
UNLOCKING THE POTENTIAL OF FTTH IN A COMPETITIVE LANDSCAPE SOFTWARE-DEFINED ACCESS NETWORKS The rush to roll out FTTH coverage and provide a range of services has created a number of issues for network operators, including network overbuild, demands for higher bandwidth, lower latency, and the need to control costs. In this article, Filip De Greve , Product marketing Director for Nokia Fixed Networks explains how Software-Defined Access Networks (SDAN) can meet these, and many other challenges.
I n the fast-evolving world of latency connectivity. Its unparalleled capacity to meet the demands of our increasingly connected digital world has attracted a surge of investment from both established operators and new entrants. However, this momentum has led to unforeseen challenges: network overbuild, market fragmentation, and shrinking profit margins. As the FTTH landscape becomes more crowded and complex, operators are seeking innovative solutions to maintain their competitive edge and ensure sustainable growth. Enter software-defined access networks, which promise to transform how FTTH networks are designed, deployed, and managed. By leveraging the principles of software-defined broadband, fibre-to-the-home (FTTH) has emerged as the gold standard for high-speed, low- networking (SDN), cloud platforms, and network automation, SDAN offers a path to increased automation, enhanced operational efficiency, and new revenue streams. As a result, it can help FTTH operators navigate the challenges of today’s market while positioning themselves for future success. THE FTTH LANDSCAPE The appeal of FTTH is clear. Applications requiring higher bandwidth and lower latencies such as cloud gaming, 4K/8K video streaming, and augmented reality are continually becoming more
Figure 1
prevalent, increasing its demand. FTTH’s future-proof infrastructure, technology- leading sustainability, and comparatively low operating costs make it an attractive investment option for those looking to capitalise on this trend. However, the push to deploy FTTH has led to some unintended consequences. Multiple operators are now competing for the same finite pool of customers due to high levels of network overbuild across markets. This is particularly evident in countries like the U.K., where over 100 alternative network operators (altnets) are active, many with ambitions
to pass just 2% or less of total national premises. This fragmentation creates several challenges including increased competition and pricing pressure (leading to falling margins), inefficiencies due to duplicated infrastructure, and difficulties in achieving economies of scale, particularly for smaller operators. The traditional approach to network management, with its reliance on manual processes and siloed systems, is ill- equipped to handle the complexities of this new landscape. This is where SDAN comes into play.
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FILIP DE GREVE SDAN
SDAN IS A GAME-CHANGER FOR BROADBAND OPERATORS At its core, SDAN extends the principles of SDN to the access network, creating a more flexible, programmable, and automated infrastructure. This approach offers several key benefits for FTTH operators. 1.Reduced operational expenses (OpEx) One of the most immediate and tangible benefits of SDAN is its ability
LOOKING AHEAD SDAN will play an increasingly important role in the FTTH landscape. By enabling greater automation, flexibility, and service innovation, SDAN helps operators address the immediate challenges of network overbuild and margin pressure while also better positioning them for future growth. We can even expect to see SDAN enabling more advanced use cases, such as ultra-low latency services, application-aware network optimisation, or deeper integration with edge computing resources for improved service delivery. In the face of increasing competition and market fragmentation, SDAN offers a set of opportunities for differentiation, cost reduction and revenue generation, hence maximising the return on investment in an FTTH infrastructure. A shift to SDAN not only addresses the immediate challenges of today’s market but also positions operators to capitalise on the emerging opportunities of our increasingly connected world.
These could include premium residential packages designed for gaming or work from home performance needs; business services with stringent SLAs and on- demand bandwidth scaling; 5G mobile transport, backhaul, mid-haul and even front-haul; wholesale services that allow virtual network operators (VNOs) to offer their own branded services over a single fibre infrastructure. These differentiated services not only command higher prices but also help operators stand out in a crowded market. 5. Flexible wholesale platform For infrastructure providers, SDAN opens up new possibilities in the wholesale market. By creating a more flexible, programmable network environment, SDAN enables innovative Network-as- a-Service (NaaS) models. These models allow infrastructure providers to offer virtual network slices to multiple service providers, with each service provider tenant able to dynamically provision and manage their own services. Wholesalers can also look at creating new partnership opportunities with content providers and other digital players providing services over a dedicated virtual network slice. This approach can help smaller operators achieve greater scale and reach, while also maximising the utilisation and monetisation of their network assets. CHALLENGES AND CONSIDERATIONS OF IMPLEMENTING SDAN While the benefits of SDAN are compelling, implementation is not without its challenges. Operators considering SDAN should be aware of several key considerations. Initial investment. Transitioning to an SDAN architecture may require significant upfront investment in new hardware, software, and training. Organisational change. SDAN represents a fundamental shift in how networks are managed, requiring new skills and potentially new organisational structures. Security. As networks become more software-defined and programmable, ensuring robust security measures becomes even more critical. Standardisation. While progress has been made, further standardisation efforts are needed to ensure interoperability across different vendors and implementations. Legacy integration. For many operators, integrating SDAN with existing legacy systems and processes will be a crucial challenge. Despite these challenges, the potential benefits of SDAN make it a compelling proposition for FTTH operators looking to gain a competitive edge in today’s market.
to streamline network operations and reduce OpEx. Specifically, by automating routine tasks such as service provisioning, configuration management, and fault resolution,
SDAN significantly reduces the need for manual intervention. This not only lowers labour costs but also minimises human error, leading to more reliable network performance. For example, SDAN enables zero- touch provisioning, allowing new services to be activated without the need for on-site visits. This can dramatically reduce the time and cost associated with service activation, improving both operational efficiency and customer satisfaction. 2. Enhanced network visibility and control SDAN provides operators with unprecedented visibility into their network performance and resource utilisation. Collecting and analysing near real-time telemetry data from across the network enables more proactive management and optimisation. This enhanced visibility allows operators to proactively identify and resolve issues prior to impacting service quality, utilise actual usage patterns to optimise resource allocation, and make more informed decisions about network expansion and upgrades. 3. Multi-vendor integration In today’s diverse FTTH ecosystem, operators often find themselves managing equipment from multiple suppliers. SDAN’s open and programmable interfaces make it easier to integrate and manage multi- vendor environments, thus reducing the complexity and cost associated with network heterogeneity. This flexibility also equips the network for future demands, allowing operators to more easily adopt new technologies and services as they emerge. 4. New revenue streams through service differentiation Perhaps the most exciting aspect of SDAN is its potential to enable new revenue streams through service differentiation. By leveraging network slicing and dynamic resource allocation, operators can offer a range of tailored services to meet diverse customer needs.
Filip De Greve, Product marketing Director for Nokia Fixed Networks Filip De Greve is based in Antwerp, Belgium and is Product Marketing Director for the Fixed Networks division at Nokia. In that role, he is focused on the go-to-market for innovative fixed access broadband solutions. Filip has over 20 years’ experience in the telecommunications industry. He previously held various roles on service provider and supplier side. As subject matter and project management expert, he has extensive experience in providing leadership in technical consultancy, project management, customer delivery, program office and product marketing. Filip holds a Ph.D. in the Telecommunications and Information Technology from the University of Ghent, Belgium.
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