DR JESS BROWN µ LED BASED INTERCONNECTS
MULTI-TERABIT µLED BASED INTERCONNECTS: UNLEASHING THE POTENTIAL OF HPC AND AI. The demand for processing power in HPC (High Performance Computing), AI (Artificial Intelligence) and ML (Machine Learning) is increasing at an unprecedented rate and although Moore’s law isn’t happening anymore, by its strictest definition, it is still delivering steady improvements in processor performance, albeit at a slower pace. However, the same improvements are not being seen for the chip-to-chip and chip- to-memory interconnect technology, where there is an ever-widening gap between the needs and the reality, writes Dr Jess Brown , Business Development, Avicena.
T he growth in Large (HBM) stacks, as shown in Figure 1. In fact, over the last 5 years LLM parameter count has grown by several orders of magnitude, whereas HBM memory bandwidth has only grown by one order of magnitude. Electrical interconnects have fundamental limits in terms of reach, size and power efficiency, especially at higher data rates, which is causing this disparity. Therefore, there is a need for low power, compact, short-reach, fast link technologies at a reasonable price point. This article delves into the revolutionary realm of optical links based on GaN µLEDs, offering a transformative approach to chip-to-chip interconnects that promise unparalleled levels of ultra- low power consumption, exceptional bandwidth density, and minimal latency, which is in stark contrast to existing SerDes-based solutions. Language Models (LLMs) has completely outpaced the increase in memory bandwidth for in-package high-bandwidth memory INTERCONNECTS: THE OPTIONS There are two types of interconnect base technologies available: electrical and optical. The diagram below (Figure 2) shows a Figure-of-Merit (FoM) for these two types of technology in different configurations. The FoM plots the product of bandwidth density and energy efficiency against link reach, from 0.1mm to 1,000m. For short reach communications (<10cm) electrical links still currently offer the best performance, whereas for long distance communications (>10m), conventional optical technologies offer the best
Figure 1: LLM Parameter Count Outpacing Memory Bandwidth.
lane, which adds a significant overhead in terms of power. Therefore, there is currently a gap between electrical and existing optical solutions, since these technologies cannot provide an optimum solution for on-board data transfer, typically in the 1cm to 10m distance, which is the range for most chip-to-chip interconnects. Avicena’s technology can fill this void and provide advantages with an optical µLED based interconnect chiplet, offering ultra-fast, low-power interconnects that bridge the gap between internal processing performance and chip-to-chip communications, for interconnects that reach up to 10m. TO SERDES OR NOT TO SERDES Distributed data processing needs high speed data transfer between ICs, whether that is between the processors, between the processors and memory, or both.
performance, but for the middle range of 1cm to 10m neither offers optimum performance. Existing multi-mode Vertical-Cavity Surface-Emitting Laser (VCSEL) based links, although well suited for distances up to 100m, are not ideal for shorter optical interconnects, primarily because high-density processors run at elevated temperatures and VCSELs have a limited tolerance for high temperature operation. Silicon Photonics (SiPh) represent another optical link technology under development and evaluation. However, these were originally developed for medium to long-haul applications, which translates to SiPh interconnects having poor efficiency performance (>5pJ/bit) for short reach interconnects. Moreover, both VCSEL and SiPh based links typically use Serialisers/De-serialisers (SerDes), discussed in the next section, to achieve the high link bandwidth of > 100Gbps per
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| ISSUE 38 | Q3 2024
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