DR JESS BROWN µ LED BASED INTERCONNECTS
individual µLED link or provide a simple muxing/demuxing function to keep latency and energy consumption to a minimum. A prime candidate for the electrical interface is the Universal Chiplet Interface Express (UCIe) which is gaining broad industry support, but other protocols like BoW or the emerging UALink are possible as well. Table 1 compares the advantages and disadvantages of parallel versus SerDes as well as the option of Avicena’s µLED optical solution and it can be seen here that Avicena’s LightBundle solution offers the best solution for chip-to-chip communications and interconnects.
Figure 2: The merit for bandwidth density and energy efficiency vs reach.
bundle to the matching array of PDs on the corresponding receiver transceiver ASIC and vice versa. A typical LightBundle link has a few hundred channels each operating at a few Gbps, providing aggregate throughputs of > 1Tbps per link. The modest per-channel speeds are well- matched to typical IC clock speeds and obviate the need for SerDes and enable the most efficient optical links at <1pJ/bit. GaN
Parallel and serial communications are the two options to transfer data between these chips. Parallel data transfer requires multiple connections between ICs, whereas serial data transfer only needs one pair of connections. On-chip communications is typically completed in a parallel format, so to enable serial interconnects a Serialiser-Deserialiser (SerDes) function block providing parallel to serial and serial-to-parallel conversion is required to enable serial communication between the two blocks. The transmitter section is a parallel to serial converter and the receiver section is a serial to parallel converter and most devices offer full-duplex operation, i.e. data in both directions at the same time. The reason for SerDes is to reduce the number of data paths needed to transmit data (and the associated number of connecting pins or wires) while achieving high link bandwidth. It additionally addresses other issues that come with transmitting parallel data electrically, such as susceptibility to electromagnetic interference and the likelihood of clock timing skew. A SerDes chip might also include an encoder, clock multiplier unit, physical coding sub-block, clock and data recovery unit, input and output staging areas, Forward Error Correction (FEC) blocks and other components. For long distance optical links there are clear advantages for using SerDes based interconnects because they minimise the number of costly, laser- based transmitters. However, when connecting ICs over distances of up to a few meters, there are clear advantages of using parallel links because ICs feature wide and relatively slow buses with clock speeds of a few Gbps internally. Avicena have developed an optical solution, using µLEDs, that overcome the disadvantages of SerDes, but still employ optical technology to gain all the associated benefits. Removing the need for SerDes, Avicena’s LightBundle TM consists of an array of GaN µLEDs and Si PDs bonded to a transceiver ASIC. The µLEDs are connected via a fibre
Table 1 Comparison of Parallel, Serial and µLED Optical Interconnect Solutions.
CONCLUSION Due to the limitations of traditional SerDes based optical interconnects the HPC, AI and IC industry is constantly evaluating innovative solutions to enable high bandwidth density, high energy efficiency and low latency interconnects for short to intermediate reach of up to a few meters. µLED technology, renowned for its application in high-resolution displays and lighting systems, has demonstrated the potential to redefine the landscape of data communication at the chip level. By combining the intrinsic advantages of light as a medium for data transmission with the 2D layout of LED arrays, µLED based optical links present a
µLEDs are already used in free-space Visible Light Communications (VLC), but at limited data rates. Avicena have managed to develop µLEDs that can operate at data rates of over 10Gbps. With this patented technology it has been demonstrated that not only can these µLEDs be modulated at high data rates, but they can also achieve bandwidth densities of > 2Tbps/mm with a power efficiency of < 1pJ/bit. The LightBundle transceiver chiplet can be either co-packaged with the processor using a silicon interposer or an organic substrate or it can be placed on the board and connected to the processor IC package via PCB traces. The only thing that changes in the different applications is the electrical interface between the LightBundle IC and the processor IC. Fundamentally, any electrical interface can be supported by the LightBundle interconnect. The LightBundle transceiver ASIC will convert the electrical data format to match the optical µLED transmission format. Parallel electrical interfaces are best suited to work in combination with the parallel optical µLED array interface of the LightBundle chiplet since no power hungry SerDes will be needed. The IC will either match the electrical lane rate to the data rate of each
ground-breaking avenue for achieving previously unattainable levels of performance in
interconnect architectures.
Dr Jess Brown, Business Development, Avicena.
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ISSUE 38 | Q3 2024
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