Process News Spring 2015 | OI Plasma Technology


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A Newsletter from Oxford Instruments Plasma Technology



Welcome to this issue of PROCESS NEWS


2/3/4 Role of Plasma Enhanced Chemical Vapour Deposition (PECVD) in Thin Film Silicon Photovoltaics 4 One of the largest semiconductor companies in Europe signs agreement for multiple Failure Analysis systems from Oxford Instruments


Getting a grip on sapphire etching: Novel clamping of sapphire looks to unleash brighter, cheaper LEDs Micro-and nanopillar patterning of GaN layer using an Oxford Instruments plasma etching system World leading graphene research at The University of Manchester uses our tools



9 Introducing the Nanofab 1200 10/11 Direct comparison of the performance of and Cr 12/13 2D plenary sessions attracted enormous interest at recent Beijing Nanotechnology Seminar 13 Facilitating a “New Era of Science” at CUNY, USA 14/15 Novel silicon nitride ICP etching process with high selectivity over silicon dioxide for gate spacers 16 Check out our Upgrades! 16 We’re flexible with our support commonly used e-beam resists during nano-scale plasma etching of Si, SiO 2

Enabling emerging applications We provide technologies that address existing and emerging applications in nanotechnology markets. With our broad process and application portfolio, our technologies enable many of the applications identified today and those of tomorrow. Look inside this issue to find out more...


Role of plasma enhanced chemical vapour deposition (PECVD) in thin film silicon photovoltaics

Dr Sekhar Bhattacharya, Dr Balai Bhargav, Mr Nafis Ahmed, Mr Balaji Chandra and Mr Arrokiya Doss, SSN Research Centre, Chennai-603110, INDIA

• 0.5-2.0 Torr operating pressure and 0.02-2.0 Wcm-2 power density The Oxford Instruments Plasma Pro ® 100 system was utilised for the following applications at the SSN Research Centre: • To deposit amorphous silicon films (doped and intrinsic) for fabrication of thin film solar cell on glass • To deposit silicon nanowires In PECVD amorphous silicon (a-Si) is deposited by plasma from a mixture of SiH 4 and H 2 gases at substrate temperature of 200-3000 o C. A typical recipe for deposition of amorphous silicon is given below:

Plasma Enhanced Chemical Vapor Deposition (PECVD) is an excellent process for depositing a variety of thin films at lower temperatures. It is a process used to deposit thin films from a gaseous state to a solid state on a substrate. Chemical reactions occur after creation of plasma of the reacting gases. Since the formation

of the reactive and energetic species in the gas phase occurs by collision in the gas phase, the substrate can be maintained at a low temperature. Hence, film formation can occur on substrates at a lower temperature than is possible in the conventional CVD process. Some of the desirable properties of PECVD films are good adhesion, good step coverage and uniformity of deposition. Some of the popular applications of PECVD include deposition of passive and active waveguide layers, dielectric films such as silicon dioxide, low stress and low temperature silicon nitride, amorphous silicon and silicon carbide.


4 flow = 20 sccm , H 2

flow = 60 sccm, Process pressure =

1000 mTorr,

Substrate temperature = 200 C, Plasma power = 31 mW/cm 2 .

If doped amorphous silicon is to be deposited then B 2 H 6 flow of 1 - 2 sccm or PH 3 flow of 1 - 2 sccm is introduced into the process chamber for P and N doping respectively. The structure of an amorphous silicon thin film solar cell is given below. Substrate is a transparent conducting oxide (TCO) coated glass on which P-I-N amorphous silicon layers are deposited by PECVD followed by metallisation in a vacuum thermal evaporator.

P a-Si layer

I a-Si layer

N a-Si layer


4 : 20 sccm


4 : 20 sccm


4 : 20 sccm



6 :1.2 sccm


3 : 1.5 sccm


PECVD Reactor: Oxford Instruments Plasma Pro 100 system


2 : 100 sccm


2 : 100 sccm


2 : 100 sccm

The key features of the system are: • Top electrode RF driven (13.56 MHz) • Substrate is transferred from loadlock and sits directly on heated electrode • Gas injected into process chamber via top “Showerhead”

20-30 nm

300-350 nm

30-40 nm

Silicon nanowires can be made by PECVD by VLS Mechanism. The vapor-liquid-solid method (VLS) is a mechanism for the growth of one-dimensional structures, such as nanowire, from chemical vapor deposition.



Al N a-Si

I a-Si

P a-Si






The schematic structure of amorphous silicon thin film solar cell

The actual solar cell (left) with I-V plot (right) under 1.5M sun

becoming energetically unfavorable, and nanometer-sized particles act to minimize their surface energy by forming droplets. 4. Si has a much higher melting point (~1414 °C) than that of the eutectic alloy, therefore Si atoms precipitate out of the supersaturated liquid-alloy droplet at the liquid-alloy/solid-Si interface and the droplet rises from the surface. Process flow:

The VLS mechanism introduces a catalytic liquid alloy phase which can rapidly adsorb a vapor to supersaturation levels from which crystal growth can subsequently occur from nucleated seeds at the liquid-solid interface. The physical characteristics of nanowires grown in this manner depend, in a controllable way, upon the size and physical properties of the liquid alloy. For the growth of silicon nanowires by PECVD the process is as follows: 2. The wafer is annealed at temperatures higher than the Metal-Si eutectic point, creating Metal-Si alloy droplets on the wafer surface (the thicker the Metal film, the larger the droplets). Mixing Metal with Si greatly reduces the melting temperature of the alloy as compared to the alloy constituents. For eg, The melting temperature of the Au-Si alloy reaches a minimum (~363 °C) when the ratio of its constituents is 4:1 Au-Si, also known as the Au-Si eutectic point. 3. One-dimensional nanowires are then grown by a liquid metal-alloy droplet-catalyzed chemical vapor deposition process. Metal-Si droplets on the surface of the substrate act to lower the activation energy of normal vapor-solid growth. However, Au particles can form Au-Si eutectic droplets at temperatures above 363 °C and adsorb Si from the vapor state (due to the fact that Au can form a solid-solution with all Si concentrations up to 100%) until reaching a supersaturated state of Si in Metal. Furthermore, nanosized Metal-Si droplets have much lower melting points due to the fact that the surface area-to-volume ratio is increasing, 1. A thin (~ 1-5 nm) metal film is deposited onto a silicon (Si) wafer substrate by sputter deposition or thermal evaporation.

Substrate cleaning RCA cleaning with Piranha, HF, and DI water

Thin film deposition Deposition of metal thin film catalyst by PVD

Annealing and characterisation of metal film At temperature higher than metal-Si eutectic temperature so that the thin film tears into nanodroplets of the metal-Si alloy PECVD Silane gas is passed through the chamber for nanodroplets to adsorb Si atoms Nanowire formation The nanodroplet catalyses the growth of nanowire and can be found at the tip of the wire Characterisation SEM/Raman analysis, reflectance spectrum studies, thickness measurement of nanowire layer

Continued overleaf


Role of Plasma Enhanced Chemical Vapour Deposition (PECVD) in Thin Film Silicon Photovoltaics.. . continued

One of the largest semiconductor companies in Europe signs agreement for multiple Failure Analysis systems from Oxford Instruments We’ve signed an agreement with one of the largest semiconductor companies in Europe for the supply of multiple Failure Analysis (FA) systems, to be installed in its manufacturing sites globally over a period of two years. The first system orders have already been placed for two Plasma Pro ® 80 ICP 65 systems, for sites in Europe and Asia. These systems, for single dies or chips up to 200mm wafers, offer industry leading high density plasma sources and ultra low plasma damage.

Silicon nanowires grown by PECVD with silane and argon gas mixture using gold as metal catalyst on silicon substrate

Silicon nanowires grown by PECVD with silane gas using gold as metal catalyst on sapphire substrate

The company needed high specification equipment for FA to replace their existing long-running installed base, consisting mainly of Oxford Instruments’ systems. After a stringent selection process they decided once again to choose our company. The requirements are for systems offering front and back end removal processes. These applications for isotropic/anisotropic back-etching include processes for polyimide and passivation, IMD/ILD materials and low-k Oxide. Also Poly-Si etching, removal of thin active Si layers, selectivity control for the removal of SiO 2 /SiNx spacers, and Si-backside removal / thinning process are part of the supplied processes. We will provide all this in one compact tool, in addition to the comprehensive global service and support required.

Raman spectrum of SiNW recorded at room temperature. The ultra-sharp pointed SiNW has a peak centered at 501 cm- 1 .

Dr Sekhar Bhattacharya was a guest speaker at the Oxford Instruments Nanotechnology Tools Seminar held in Calcutta in November 2014.


Getting a grip on sapphire etching: Novel clamping of sapphire looks to unleash brighter, cheaper LEDs

By Dr Mark Dineen, Oxford Instruments From an article published in Compound Semiconductor January/February 2015 edition

Patterned sapphire substrates or PSS have been widely adopted by LED manufacturers striving to make cheaper devices that emit more light. Oxford Instruments has developed

the Plasma Pro 100 Polaris tool to etch highly controlled PSS patterns in an efficient manner.

With the drive to improve device dollars per lumen LED manufacturers are constantly looking for innovative solutions. Etching a specific pattern into the sapphire wafer prior to MOCVD growth is such an innovation and it is becoming standard because it delivers two key benefits: • It increases the fraction of light emitted from the device, thanks to the controlled texture

• It leads to a lower density of defects within the film, thanks to growth on a three-dimensional landscape that spurs earlier coalescence of GaN epitaxial islands during MOCVD growth The downside of turning to patterned sapphire is that etching this material into useful patterns is not easy. There is a processing cost involved, and this must be low enough to not negate the benefit associated with increased LED performance.

Through specially developed hardware the

Plasma Pro 100 Polaris tool etches the PSS wafer and gives the pattern control required to provide maximum light output.

Contact us at to receive the full article or go to


Micro-and nanopillar patterning of GaN layer using an Oxford Instruments plasma etching system

Dr Nagarajan Subramaniyam and Prof Markku Sopanen, Optoelectronics Group, Dept. of Micro and Nanosciences, Micronova, Aalto University, Finland

Innovations in visible (ultraviolet to near infrared) region optoelectronic devices are revolutionizing lighting technology, as exemplified by Nobel prizes given to the Gallium nitride (GaN) based light emitting diodes (LEDs) in 2014. These innovations are widely used in modern smart phones and energy efficient light bulbs. Commercially available white LEDs are a combination of GaN based LEDs in the blue or UV wavelength with appropriate phosphors to produce a desired white light. The efficacy of GaN light sources demonstrated in recent years has already exceeded 245 lm/W for white light. Although GaN based LEDs are commercially available on the market, there are still many challenges needing to be addressed. The light extraction efficiency, green/yellow gap and high dislocation density on sapphire substrates are major challenges for future high efficiency LEDs. In order to reduce the dislocation density and

Dr Nagarajan was a guest speaker at the Oxford Instruments Nanotechnology Tools Seminars held in Calcutta and New Delhi in November 2014

increase the light extraction efficiency, micro- and nanopillar patterned a GaN template is used. GaN micro- and nanopillar patterning can be created by a top-down etch process using Oxford Instruments’ inductively coupled plasma-reactive ion etching (ICP-RIE) Plasmalab system. Fig.1 a) shows the scanning electron microscopy (SEM) image of micropillar patterned GaN template using Oxford Instruments’ ICP-RIE system from a 3-µm thick GaN layer [1]. GaN micropillar structures were arranged by conventional photolithography methods and etched down to the sapphire substrate. The etching conditions were 15 sccm of Cl 2 and 2.5 sccm of Ar with a total pressure of 4 mTorr. The RF power was kept as 150W while 450W of ICP power was used during the etching process. The pillar diameter, height and pillar center to center distances were 2µm, 3µm and 4μm, respectively. A very smooth and vertical sidewall is achieved by optimizing the etching parameters. The etched GaN micropillar quality is studied by a confocal Raman mapping technique. Figure 1 b) shows the top view confocal




061 to achieve high efficient light emitting diodes. Figure 2 b) shows the high-crystalline InGaN active region grown on (0001) top facet, six smooth tilted facets of {1-101}, and {10- 10} m planes.

Raman intensity imaging of etched GaN micropillars. The full- width half maximum of E 2 (high) phonon value is 4.2±0.5 cm- 1 which indicates the high-crystalline quality of GaN micropillars fabricated by Oxford Instruments ICP-RIE [2]. The etched GaN micropillar template is used to grow 5-µm thick GaN layer and followed by InGaN/GaN multi-quantum well (MQWs) based light emitting diodes (LEDs). The optical output performance is dramatically increased in micropillar patterned GaN template compared to the normal GaN template as shown in Fig. 1c). Figure 1 . a) SEM image of patterned GaN micropillars b) Confocal Raman intensity imaging of GaN micropillars c) Light output performance of InGaN/GaN quantum-well on patterned GaN micropillar at different excitation powers.

In conclusion, micro- and nanopillar patterned GaN template etched by Oxford Instruments' ICP-RIE have wide application in the field of optoelectronic devices.



Figure 2 a) SEM image of etched GaN nanopillars using ICP-RIE b) SEM image of re-grown InGaN/GaN MQWs on etched GaN nanopillar template.


GaN nanostructures have been proposed for highly efficient future nano-optoelectronic devices. Figure 2a) shows the SEM image of GaN nanopillars fabricated by self-assembled Ni mask and ICP-RIE etching. The strain distribution of individual GaN nanopillar is studied by a confocal Raman mapping technique [3]. The GaN nanopillar template is used to re-grow InGaN/ GaN multi-quantum wells (MQWs) on different crystal planes

References: 1. O. Svensk, M. Ali, L. Riuttanen, P. T. Törmä, S. Sintonen, S. Suihkonen, M. Sopanen and H. Lipsanen. J. Crys. Grow. 370, 42-45 (2013). 2. S. Nagarajan, O. Svensk, M. Ali, G. Naresh-Kumar, C. Trager-Cowan, S. Suihkonen, M. Sopanen and H. Lipsanen. Appl. Phys. Lett. 103, 012102 (2013). 3. S. Nagarajan, O. Svensk, L. Lehtola, H. Lipsanen and M. Sopanen. Appl. Phys. Lett. 104, 151906 (2014).


The University of Manchester uses our tools for world leading graphene research

Ground breaking research into graphene and other 2D materials will take place at The University of Manchester’s new National Graphene Institute using multiple, recently purchased, plasma etch and deposition systems from Oxford Instruments. These semiconductor processing tools will facilitate the potential applications of these materials in novel electronics and optoelectronics applications. We were chosen to supply Plasma Pro ® PECVD and ICP-CVD deposition tools, and Plasma Pro ICP etch tools, that will enable the fabrication of tailored substrates for graphene such as SiN membranes which are useful for both fundamental and applied research on graphene and 2D materials.

“Our £61 million facility is being designed with the goal to be the world-leading research and incubator centre dedicated to the development of graphene, helping the UK to remain at the forefront of the commercialisation of this revolutionary material” , comments Dr Ernie Hill, Senior Lecturer & Assistant Director of The Manchester Centre for Mesoscience & Nanotechnology,

“We chose Oxford Instruments’ tools as they could provide the breadth of high technology process solutions and hardware that our users will require to fulfil their research. The excellent support offered will ensure maximum uptime of the systems, which is critical for our users.”


Introducing the Nanofab 1200

Growth of 2D materials and other nanostructures

Chemical Vapour Deposition (CVD) has been one of the most successful techniques for the fabrication of nanostructured materials such as graphene, carbon nanotubes and other 1D and 2D nanomaterials. Oxford Instruments offers highly flexible tools and proven processes to deliver growth of nanostructured materials as well as produce a broad range of Plasma Enhanced CVD (PECVD) films. The Nanofab 1200 is our latest CVD/PECVD system that is ideal for this field of research as it combines several essential features for high performance growth. • Cold wall design with showerhead based uniform precursor delivery • Remote plasma option via ICP • Vacuum load lock for quick sample exchange • Excellent temperature uniformity • Optional liquid/solid source delivery system • Capable of processing samples with sizes ranging from small pieces to 200mm wafers

• Multiple viewports for diagnostics Nanostructured materials: Graphene, hBN, Carbon Nanotubes, Si, Ge, ZnO, MoS 2 , WS 2 , Ga 2 O 3 , GaN, GaAs, GaP, InP, InN PECVD Films: SiO2, SiNx, a-Si, SiON, poly-Si, SiC

Cross-sectional TEM image of a hBN film on Ni substrate grown by CVD on the Nanofab1200 system. (TEM image courtesy of Dr. Peter Werner, Max Planck Institute of Microstructure Physics)

Remote Plasma ICPCVD

Raman Spectrum of Graphene grown on Ni foil on the Nanofab 1000 Agile

Nanocrystalline graphene film grown on 150 mm wafer via PECVD. Results obtained using Nanofab 1000 Agile 1 .


Direct comparison of the performance of commonly used e-beam resists during nano-scale plasma etching of Si, SiO 2 and Cr Andy Goodyear 1 , Monika Boettcher 2 , Ines Stolberg 2 , Mike Cooke 1 1) Oxford Instruments Plasma Technology, North End, Yatton, Bristol, BS49 4AP, UK 2) Vistec Electron Beam GmbH, Ilmstrasse 4, D-07743 Jena, Germany

Electron beam writing remains one of the reference pattern generation techniques, and plasma etching continues to underpin pattern transfer. We report a systematic study of the plasma etch resistance of several e-beam resists, both negative and positive as well as classical and Chemically Amplified Resists: HSQ (Dow Corning), PMMA (Allresist GmbH), AR-P6200 (Allresist GmbH), ZEP520 (Zeon Corporation), CAN028 (TOK), CAP164 (TOK), and an additional pCAR (non-disclosed provider). Their behaviour under plasma exposure to various nano-scale plasma etch chemistries was examined (SF 6 /C 4 F 8 ICP silicon etch, CHF 3 /Ar RIE SiO 2 etch, Cl 2 /O 2 RIE and ICP chrome etch, and HBr ICP silicon etch). Samples of each resist type were etched simultaneously to provide a direct comparison of their etch resistance. E-beam exposures were carried out on a Vistec SB254 (Vistec Electron Beam GmbH). This is a Variable Shaped Beam system operating at 50 kV which is applied for patterning resist masks for Electron Beam Direct Write (EBDW) on Silicon and III-V semiconductor materials, for Mask Writing on Quartz substrates, as well as for optical and emerging applications. Etching was carried out in a Plasma Pro 100 Cobra etch tool from Oxford Instruments Plasma Technology. Feature widths down to 30nm were e-beam written. Silicon trench widths down to 30nm were etched for most of the resist types, however it was decided to compare etch profiles using 50nm wide features in order to provide a full set of SEM data. The etch processes were not specifically optimised for selectivity, so should be representative of typical results. HSQ performed well in all processes except for SiO 2 etching, and produced high resolution patterns, so would be the recommended resist if the increased processing requirements and high exposure dose can be tolerated.. The three chemically amplified resists (CAP164,

Fig 1 . Selectivity comparison for various process types

Fig 2 . Si etch profile using SF 6 /C 4 F 8

with HSQ resist

CAN028, pCAR) also showed good selectivity performance and good etch profiles, with CAN028 giving the higher selectivity for most processes. Of the other resists (AR-P6200, ZEP520, PMMA), AR-P6200 produced the best etch profiles, although this may be because it was a slightly thicker layer. The etch selectivity and etch profiles of all tested resists were significantly better than PMMA, and (apart from HSQ) required a lower exposure dose.


(a) 061


Fig 4 . Si etch profiles using HBr ICP

Fig 3 . Pre-etch resist profiles

When comparing the Silicon etch profiles, the SF 6 /C 4 F 8 etch chemistry typically resulted in some lateral erosion of the resist, which produced a sloping of the trench sidewall for resists which had a lower selectivity or a poor starting profile, whereas this was not so evident for HBr etching.

Fig 5 . Si etch profiles using SF 6 /C 4 F 8


To summarise, the results give an indication of the etch selectivity and profile that can be achieved with various e-beam resists and etch chemistries. Depending on the application and the resist type, the resist process and etch chemistry should be carefully selected to produce the optimum result.

From a paper presented at SPIE Advanced Lithography 2015


Plasma Processes for Emerging Silicon-based MEMS, NEMS and Packaging Applications

Mark McNie, Principal Applications Engineer, Oxford Instruments

Plasma processes are important for emerging silicon-based micro- electro-mechanical systems (MEMS), nano-electro-mechanical systems (NEMS) and packaging applications. A one process per device rule is typical. Synergies may be found as most are produced using a 2.5D approach -sequential deposition, lithography and etch cycles. Plasma processes are critical in enabling dry deposition and etch steps for manufacturable devices. Increasingly they are being adopted in lithography (nanoimprint) and bonding process steps. Plasma processes can be divided into the following broad families: • Chemical vapour deposition (CVD) • Etch (physically-driven) • Etch (chemically-driven) • Surface functionalisation The merits of each plasma technique and their application to emerging devices are summarised below.. Plasma-enhanced chemical vapour deposition (PECVD) of dielectrics and silicon is widely used to enable lower temperature processes than conventional low pressure CVD. Adjustment of deposition parameters can tune stress, chemical resistance, optical properties and wear characteristics for different application requirements. At higher temperatures, plasma-assisted nanogrowth of carbon nanotubes and 2D materials (e.g. graphene) are emerging technologies. Conversely, inductively coupled plasma CVD (ICP-CVD) is attracting interest to enable high quality films at lower temperatures. Plasma-assisted ALD enables thin and uniform layers of a wider range of materials to be grown and, similarly, high quality films at lower processing temperatures. Plasma-based PVD processes include sputtering and ion beam deposition. The former is a standard technique for metallisation. Al-based schemes are typical in the silicon IC industry but different metallisations (e.g. Au or Pt-based) may be required for sensors to give HF resistance or physical contacts. Ion beam deposition is often used for complex multilayer stacks. Physically-driven etch processes require ions to provide enough energy to enable a chemical reaction or to physically break bonds at the wafer surface. Conversely, chemically-driven etch processes spontaneously • Atomic layer deposition (ALD) • Physical vapour deposition (PVD)

react but require passivation species to obtain directionality (anisotropy). Ion beam etch processes enable non-volatile materials to be physically etched, such as Vanadium Oxide for uncooled infra red detectors. If the substrate is tilted then non-vertical structures, such as blazed gratings, may be realised. Plasmas may be used to clean surfaces or to create specific surface conditions for subsequent steps. This may be to passivate them, increase bond strengths at low temperatures or to subsequently functionalise them – e.g. adding hydrophobic self-assembled monolayers (SAMs) in MEMS microphones or for bio-coatings for biomedical devices. The process step common to the majority of MEMS devices today is the Bosch silicon etch process. This uses a repeating sequence of PECVD deposition, physical etch for passivation removal and chemical etch that results in a high rate, highly vertical and highly selective silicon etch although the cyclic nature results in a characteristic sidewall roughness (scalloping). High aspect ratio structures may be realised and the process is not sensitive to crystal orientation (which limits geometries with anisotropic wet etchants). The majority of physical sensing devices are based on sub-70μm depth features. Trends are towards higher aspect ratios for enhanced performance and smaller footprint whilst maintaining throughput. Increasingly, large cavities are also being etched for subsequent chip or wafer scale packaging and sensor structures may comprise multi-wafer stacks with one of more having through wafer etches (300-750μm). With the move to multi-wafer structures comes the challenge of interconnect. Monolithically integrated devices are key to some high volume MEMS applications; however, the most common approach is to use hybrid integration – allowing separate optimisation of readout IC and MEMS devices. Increasingly solutions are moving towards system-in-a-package (SiP) and system-on-a-chip (SoC) solutions. Through silicon vias (TSVs) are emerging as a key technology for this in the MEMS and IC industries. Aspect ratios are generally limited to around 10-15:1 using the Bosch process in production. This is typically followed by dielectric isolation (e.g. by TEOS) and barrier / seed metal layers (e.g. by ALD) prior to electroplating. At the nanoscale, etching becomes more challenging. The Bosch process is less well suited due to the finite sidewall scallop size and reduced rates / selectivity.


We recently won an order for Plasma Pro 100 ICP and PECVD systems, and Plasma Pro 80 RIE tools, that will offer an extensive range of process capability for an impressive new facility which is being developed for the colleges of The City University of New York. Facilitating a “New Era of Science” at CUNY, USA

Typically it is not used below 500nm feature sizes

although 100nm features have been demonstrated. A continuously passivating process

has smooth sidewalls but a lower rate, selectivity and aspect ratio capability at room temperature. Moving to cryogenic temperatures enables the highest rate, selectivity and aspect ratios to be achieved and can realise 10nm trench features. In summary, emerging applications in silicon-based MEMS, NEMS and packaging require a diverse range of plasma processes. These in turn need a flexible toolset to address multiple different requirements on a single line to get volume scaling.

Plasma Pro 80 RIE tool

Top to bottom: TEOS deposited in a through silicon via (TSV); 10μm TSV features etched to 120μm depth in a Bosch process.

“The CUNY Advanced Science Research Center (ASRC) will bring the University to a landmark moment in its decade-long, multi- billion-dollar commitment to becoming a national leader in visionary scientific research of vital, real-world consequence,” says Vice Chancellor for Research, Prof Gillian Small. “The ASRC and its core facilities, including the nanofabrication facility, expand on the research capabilities of CUNY and New York City. The Oxford Instruments systems offer the high technology, leading edge solutions that fit with our very high specifications”

This article is based on an abstract for an invited paper at the 227th ECS Meeting. The full article may be downloaded from the ECS digital library


Novel silicon nitride ICP etching process with high selectivity over silicon dioxide for gate spacers ili nitride ICP etching process wit high i it ver s licon dioxide for gate spacers

Colin C. Welch1 and Vincent J. Genova2 1 and Vincent J. Genova 2

A novel difluoromethane (CH 2 F 2 )-sulfur hexafluoride (SF 6 )- nitrogen (N 2 ) inductively coupled plasma (ICP) was investigated with the aim of developing a silicon nitride (Si 3 N 4 ) etching

Experimental 400nm of low pressure chemical vapor deposited (LPCVD) Si 3 N 4 was grown on thermally oxidized standard silicon wafers and patterned with photoresist (PR) (minimum feature sizes 1µm). Etching experiments on 1x1 cm pieces were done in a modified Oxford Instruments System 100 tool. This features a cylindrical ICP380 source, independent substrate electrode bias, mechanical clamping and helium backside pressure for good temperature control and gas introduction through a ring just above the wafer or the top of the ICP source. Experiments were formulated using a Taguchi L9 orthogonal matrix [5]. This enables a wide range of parameter space to be studied with relatively few process trials by means of an averaging procedure possible due to the symmetrical matrix properties. The input parameters were CH 2 F 2 flow rate, pressure, ICP source power and electrode bias (RIE) power. The output responses were Si 3 N 4 etch rate, selectivity over SiO 2 and selectivity over PR. Results The results of the L9 matrix are summarized below. Figure 4 shows etch rate trends for Si 3 N 4 , SiO 2 and PR. Figure 5 shows selectivity trends for Si 3 N 4 over SiO 2 and over PR. It can be seen there are trends to higher selectivity over SiO 2 as pressure and CH 2 F 2 flow rate increase, and as ICP and RIE powers decrease. through the gas ring, further stepwise process development led to a process with the following characteristics: Si3N4 etch rate 47nm/min, selectivity over SiO 2 4.7:1 and selectivity over PR 1.5:1. Figure 6 shows the Si 3 N 4 etched profile is about 80. Using these trends for guidance, and introducing CH 2 F 2

Colin Welch

process having high selectivity over silicon dioxide (SiO 2 in gate spacers. See Figure 1. Gate spacers are used in metal oxide semiconductor field effect transistors (MOSFET) in order to precisely define the channel length with an abrupt junction in modern nanoscale architectures [1]. The spacer allows the benefits of a lightly doped drain (LDD) - lower capacitance and lower electric field near the gate - without the main disadvantage of higher resistance. This is because the spacer can mask a subsequent deep source-drain implant to reduce resistance away from the gate. Silicon nitride has several advantages as a spacer material [2]. However, the etching of Si 3 N 4 spacers requires high selectivity to stop on ultrathin thin gates dielectrics with SiO 2 thickness typically less 6 nm in order to avoid etch damage and silicon substrate loss in source/drain regions. Selective etching of Si 3 N 4 over SiO 2 is inherently challenging because both materials are etched by standard fluorine gases such as CHF 3 , CF 4 , SF 6 , etc. One study used CF 4 or NF 3 highly diluted in Ar/O 2 to achieve high selectivity [3]. This was more for a nitride strip application however. Another study used CF 4 -CH 4 to achieve high selectivity [4], but the CH 4 is known to be a strongly polymerizing gas leading to short mean time to chamber clean. We screened several candidate chemistries and found CH 2 F 2 -SF 6 -N 2 to be the most promising for further investigation. ). Such a process finds application


Discussion and Conclusion Initial XPS results show CH 2 F 2 produces a low F/C ratio polymer boundary layer (actually a hydrofluorocarbon film) on the SiO 2 and Si 3 N 4 surfaces which interacts differently with each. We believe the formation of HCN etch products on Si 3 N 4 enhance its etch rate with respect to SiO 2 and hence the selectivity. The matrix shows improved selectivity with increasing CH 2 F 2 flow rate and pressure which suggests increased favourable polymer on the Si 3 N 4 surface. The use of the gas ring enhances this favourable polymer by avoiding over-fragmentation of the CH 2 F 2 molecule, while an optimum level of N 2 encourages the HCN formation. In conclusion, good initial results for selective silicon nitride etching over silicon dioxide using a novel CH 2 F 2 -SF 6 -N 2 ICP process were presented. Further work will optimize the process for even higher selectivity and straighter etched profile, test masking with SiO 2 , further elucidate the mechanism for selectivity and, finally test topographical structures realistic to spacer structures.

Figure 2: Selectivity trends for LPCVD Si 3 N 4

over thermal SiO 2


over photoresist

Figure 3: 400nm LPCVD Si 3 N 4 showing a profile of 80°

etched down to a Si substrate

Figure 1: Etch rate trends for LPCVD Si 3 N 4

, thermal SiO 2

and photoresist

References [1] R.A. Gottscho, K. Nojiri, and J. LaCara: Thin Solid Films 516, (2008), p. 3493 [2] C. Mazure, C. Gunderson, and B. Roman: Tech. Dig. Int. Electron Devices Meet. (1992), p. 893 [3] B.E.E. Kastenmeier, P. J. Matsuo, and G. S. Oehrlein: J. Vac. Sci. Technol. A 17(6), (Nov/Dec 1999), p. 3179 [4] S. Lee, J. Oh, K. Lee, and H. Sohn: J. Vac. Sci. Technol. B 28,1 (Jan/Feb 2010), p. 131 [5] G.Z. Yin and D.W. Jillie: Solid State Technology (May 1987), p. 127.


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