MAXIM KUSCHNEROV ECONOMICS
the price of a DSP is mainly governed by its volume, favoring a generic DSP approach.
FUTURE DIFFERENTIATION With white box DSP gaining traction in the market, what are the main areas for innovation in future DSPs? FlexEthernet, 400GbE and beyond – Having an ever increasing dominance of internet content providers (ICPs) in the market, 400GbE is expected to thrive relatively faster than 100GbE did. A power e cient DSP will have to scale up to line rates of up to 600Gb/s per lambda and above. The performance of analog I/Os can become a crucial di erentiator and quickly separate the wheat from the cha . Optical performance – With the reach performance of current DSPs being relatively mature, the market is about to enter the end game for ultimate advances on nonlinear equalization and forward error correction to achieve the optimum transmission reach. A smart design in this area could especially impact the ultra- long-haul and submarine markets. Horizontal integration – Over several generation of 100Gb/s DSPs, multiple stand-alone functions were integrated in single-die application-specific integrated circuits (ASICs), such as the transmitter gear box, forward error correction or OTN framing, thus lowering cost and footprint. Further integration of functionality, such as Ethernet grooming and switching could improve the e ciency of data center appliances and potentially eliminate additional chips on the board or even additional equipment. Moreover, a co- packaging of optics and electronics seems like an almost inevitable step in the future, both for colored line optics as well as for short-reach interconnects. Enabling of a new application – Di erentiation in DSPs becomes a truly powerful weapon if a chip can enable a new end-user application. One of the most striking examples was the introduction of the coherent CFP form factor with ultra-low power DSPs, which was backwards compatible to existing CFP slots in commercial router and transport equipment. Thus, a grey port for short reach interconnects could overnight become a long-haul colored interface. Developing a DSP for a coherent metro 400GbE data center switch pluggable could be the next big step, enabling massive scale in the market. Concluding, the appearance of white box 100Gb/s metro DSPs is nothing but the equivalent of a 10Gb/s XFP – a sign of maturity at this data rate, but not the final verdict for higher data rates at 400GbE and above. The combination of increasing development costs and falling prices for communication equipment means that the most important aspect for DSP economics will be scale, which can only be achieved by a few selected leaders in DSP development commanding a high market volume. Further maturity and consolidation in this market segment will thus be inevitable.
Economics of coherent DSPs in the age of White Box 100G
Increasing development costs and falling prices of networking kit means that scalability of digital signal processing is critical. Maxim Kuschernov argues that this means market consolidation is inevitable.
DR. MAXIM KUSCHNEROV
I n 2016 AT&T announced its OpenROADM initiative with the target of a SDN-enabled, multi-vendor interoperable and disaggregated metro network. Here, an important aspect is a generic 100Gb/s metro interface, a requirement shared with the TeraStream architecture developed by Deutsche Telekom. leading network equipment manufacturers (NEM) develop own coherent digital signal processors (DSP) in order to secure time- to-market advantage with critical features like soft-decision forward error correction (SD-FEC), 200Gb/s 16QAM line rates or integrated framing for 100GbE services. Over time, merchant silicon companies caught up with designs that were matching or even besting some of the NEMs. Fueled by the hot 100Gb/s metro market, the industry now has entered the phase of generic metro DSPs. For a straight forward transmission of 100GbE ARRIVAL OF GENERIC DSPS The beginning of coherent optics saw
or lower rate services, these chips are destined to bottom out at very low market pricing. Is this the point in time for NEMs to reconsider in-house DSP developments, betting on generic hardware, or is the path forward still dominated by di erentiation, even in the age of white box-like appliances? COST OF DSP DEVELOPMENT DSP development goes through several major steps – from high level algorithm design to hardware description language, development and integration of analog macros for host and line side I/Os, as well as the physical design of the functional blocks including verification and tool costs. The netlist is handed o to a semiconductor foundry for production. Whereas mask costs for 28nm process were in the range of $2M, the step to 16nm comes in between $5M and $7M. Overall, the development costs of such DSPs can range anywhere from $20M to $50M and above. The actual manufacturing costs for these devices are rather low and unless licenses have to be paid for 3rd party IP,
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| ISSUE 7 | Q3 2016
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