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I/O CHIPLETS FOR AI INTERCONNECT HIGH-BANDWIDTH CO-PACKAGED OPTICAL
W ith the rapidly increasing deployments of larger and larger AI clusters built with more and more GPUs in the high-bandwidth scale-up domain, interconnect based on copper cables is becoming a bottleneck due to their limited bandwidth and reach. For scale-out networks, pluggable optics has served us well and offers a scalable path with future linear optics either in pluggable form or co-packaged. However, for the scale-up fabric, we are looking for lower power and lower cost- per-bandwidth than can be supported with current optical interface solutions. In this article, we share some of Intel’s work around high-density power- efficient silicon photonics-based optical I/O chiplets that are purpose-built for AI infrastructure. The I/O chiplet is intended for co- packaging with networking SOCs or compute resources to enable the reach and capability of optical interconnects, at the power consumption of copper. The chiplet is a fully integrated optical subsystem on a single silicon photonics chip built in Intel’s fab and taking advantage of the unique capability of integrating the laser light source and optical gain on the silicon die. The PIC was fabricated on the same silicon photonics line that is volume-proven with ~10 million Tx PICs deployed in pluggable modules in datacenter networks. The I/O chiplet has 8 Tx/ Rx fiber-pairs, each carrying data on
8 wavelengths spaced at 200GHz and generated from the on-chip DFB laser- array. Designed for operation at 64Gbps modulation speed, the 64-channel optical subsystem on a chip supports 4Tbps bandwidth per direction and >100m reach. The PIC is combined in a compact die-stack with a CMOS IC containing the analog front-end, control loops and other electronics, to form a complete transceiver array. The image above shows the complete die-stack. In the initial implementation, the chiplet is a linear E/O converter that attaches to a standard high-speed SERDES interface on the host IC, but in future implementations, currently under development, the host-side interface will be based on a high-density power efficient die-to-die interface such as UCIe, for the highest density and lowest power. With this approach where the link is supported with a purpose-built SERDES and DSP optimized for the optical channel, the end-to-end link can be realized with <5pJ/b power consumption. On the path to product and volume deployment, Intel demonstrated the technology capability with an optical I/O chiplet co-packaged with an Intel CPU. The industry-first co-packaging of an optical I/O chiplet with an CPU or GPU showcased CPU-to-CPU optical PCIe Gen5 interconnect using in-package optics and pointed to the future of scaling AI infrastructure based on co- packaged optical interconnect. Scaling in bandwidth and density comes through
cost and power efficient increase in wavelength count enabled by the on- chip laser technology, and from higher modulation bandwidth to increase the bandwidth per wavelength. Transmitter PICs operating at up to 200Gbps (PAM4) have been demonstrated for Ethernet pluggable chipsets. Besides the scalability and manufacturability that comes with the on-chip lasers manufactured at wafer-scale, the technology also offers excellent control and uniformity, and highly reliable lasers with demonstrated failure rate <0.1 FIT. In summary, the bandwidth scaling challenges presented by future AI deployments call for a new class of optical network interfaces that can support high bandwidth in a more power- and cost-efficient manner than current optical interfaces. Intel has demonstrated the first implementation of a co-packaged scalable high-bandwidth I/O chiplet based on a mature, volume-proven silicon photonics technology platform. The work highlighted the capability of the silicon photonics platform, using a 64-channel PCIe gen5 PIC as demonstration vehicle, with a clear bandwidth scalability path to support the requirements of future compute systems.
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| ISSUE 42 | Q3 2025
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