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on link performance to meet the demands of 400G/lane high-speed transmission. 3. Solutions for Chirping, Dispersion, and Link Budget Issues. Building switches to be ready for the terabit generation Mark Nowell, Cisco As Switch ASIC bandwidths push into the 100’s of Tb/s, the architectures, technologies and solutions to be able to build these switches continues to evolve. This presentation will review the trends and challenges and potential solutions that are being developed to enable these high-capacity switches, which are key to building performative AI clusters. Beyond 1600ZR: Liquid cooling, advanced optics, and the evolution As the number of XPUs required for LLM training exponentially increases from tens to hundreds of thousands and power density per rack increases while total data centre power remains constant, new innovations in higher speed, low power and high-performance optical interconnects are needed. This session provides insights into the next generation of coherent pluggable transceivers that will power networks of the future, including 1600ZR, 1600ZR+ and beyond. Examples of technology readiness will be presented, from 3nm to 2nm and 18A CMOS technology nodes to 140GHz- of the pluggable Frank Chang, Ciena
suggests that PAM4 is likely a reasonable choice 448G optical interfaces, however electrical interfaces present additional challenges. This presentation analyses extensive experimental data measured using Ciena high bandwidth 3nm silicon exploring the benefits and challenges for electrical interconnect using a variety of modulation formats. The next frontier: 400G/ lane optical interconnects racing towards 1.6T/3.2T – the opportunities and challenges Jiangwei Man, Huawei Hisilicon With the release of 224G Serdes GPU and 224G Serdes 100T switching device, the 200G/lane short-reach optical interconnection technology between GPUs and switching devices is poised to enter the commercial delivery phase. As the data rates of GPUs and switching devices in AI applications continue to escalate, the short-reach optical interconnection technology will progressively evolve towards 400G/lane. This presentation will delve into the critical technologies of optoelectronic devices and links in 400G/lane short- reach optical interconnection. The focus will be on three key areas: 1. Addressing the challenges of achieving high bandwidth in EML and TFLN devices, with an emphasis on Huawei’s current design approaches and performance verification. 2. Analysing the effects of various modulation formats, including PAM-N
capable electro-optics. The foundational shift from air-cooled to liquid cooled pluggables with the 3.2T generation will also be presented, including design details recently presented at the OSFP MSA. Energy efficiency in AI applications – making sense of the multiple requirements Jeff Hutchins, Ranovus The rapid evolution of artificial intelligence (AI) is driving larger and highly interconnected clusters with the need to shuffle huge quantities of data between compute elements. The next generation of AI compute clusters will require a variety of different communication links, each satisfying a unique set of requirements. The Optical Internet Forum (OIF) is studying new electrical and optical interfaces in a variety of architectures including lower power retiming architectures such as linear and Tx retimed chip-to-optical engine interfaces that meet the hyperscalers’ requirements for scale-out and scale-up links. These innovations for energy efficient connectivity for AI compute clusters can help bring optics into the scale-up domain for the first time. Join the OIF industry expert to learn about these new energy efficient links, their requirements, the various trade offs, and the latest on the OIF’s progress on Energy Efficient Interfaces for AI compute to help build the industry’s eco-system.
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| ISSUE 42 | Q3 2025
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