INDUSTRY FOCUS PRODUCT HIGHLIGHTS 2024
The advent of Artificial Intelligence and Machine Learning is making demands on bandwidth, latency, power reduction, and speed that the communications industry has never previously experienced. True to form, and to its credit, the industry has responded, particularly in the area of optical packaging, with PICs which offer previously unimaginable performance. Here is just small sample of the many innovative products launched in 2024. 2024: AI/ML DRIVES PACKAGING INNOVATION INTEL’S 4TBPS SIPHO OCI CHIPLET
Intel has developed a 4Tbps bidirectional, fully integrated Optical Compute Interconnect (OCI) chiplet (pictured) based on its in-house Silicon Photonics technology, to address the AI infrastructure’s tremendous need for bandwidth and to enable future scalability. This OCI chiplet or tile contains a single Silicon Photonics Integrated Circuit (PIC) with integrated lasers, an electrical IC with RF
Through-Silicon-Vias (TSV), and a path to incorporate a detachable/re-usable optical connector. The OCI chiplet can be co-packaged with next-generation CPU, GPU, IPU, and other System-On- a-Chip (SOC) applications with high bandwidth demand. Intel says this first implementation paves the way toward providing multi- Terabit optical connectivity with a >4x improvement in shoreline density over PCIe Gen6, an energy efficiency
of <3pJ/bit, <10ns (+TOF) of latency, and a reach greater than 100 meters. This first OCI implementation is a 4Tbps bidirectional chiplet compatible with PCIe Gen5, supporting 64 lanes of 32 Gbps data in each direction over 10’s of meters, realised as eight fibre pairs each carrying eight DWDM wavelengths. Looking beyond this first implementation, the platform has line of sight to 32Tbps chiplets.
BROADCOM’S 51.2T CPO SWITCH
Coming on the back of news that Broadcom Inc. has extended AI optical component portfolio, the company delivered Bailly (pictured), which the company claims is the industry’s first 51.2 terabits per sec (Tbps) co-packaged optics (CPO) Ethernet switch, to its customers. The product integrates eight silicon photonics based 6.4- Tbps optical engines with Broadcom’s best-in-class StrataXGS® Tomahawk®5
switch chip. Broadcom says Bailly enables the optical interconnect to operate at 70% lower power consumption and delivers an 8x improvement in silicon area efficiency as compared to pluggable transceiver solutions. Details of the Bailly chip, were first announced at OFC 2023. Bailly integrates hundreds of optical components and hundreds of millions of transistors in a single optical engine. The high degree
of integration enables the placement of the optical engines on a common substrate with complex
logic ASICs minimising the need for signal conditioning circuitry. This allows the optical interconnect to operate at 70% lower power consumption as compared to pluggable transceivers. Bailly’s high- volume production is made possible by Broadcom’s manufacturing approach that utilises proven CMOS foundry
processes, advanced packaging technologies and a highly
automated high-density, edge- coupled fibre attach capability. Broadcom is co-designing platforms with cloud service providers (CSPs) and system integrators to accelerate adoption of CPO platforms.
AVICENA’S SCALABLE SUB-PJ/BIT CHIPLET
Avicena debuted its scalable LightBundle chiplet interconnect, which extends ultra-high density die-to-die (D2D) connections up to 10m at multi-Tbps/mm shoreline bandwidth density and sub-pJ/ bit energy efficiency. Based on Avicena’s LightBundle platform which supports shoreline density and energy efficiency, it unlocks increased performance from HPC and AI cluster
architectures. The LightBundle chiplet interconnect extends HBM and other ultra-high performance D2D connections up to 10m while dissipating < 1pJ/bit for the optical interconnect and supporting multi-Tbps/mm beachfront density. This enables GPUs and other high-performance ICs to greatly increase their total IO bandwidth, accessing vastly more HBM and relieving
inter-processor bottlenecks. The LightBundle chiplet is compatible with standard multichip packaging and supports a wide range of D2D interfaces including standard and advanced versions of UCIe and BOW. Avicena is working with selected partners on different implementations. Initial prototypes will be available in the second half of 2025.
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INDUSTRY FOCUS 2024/2025
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