JOHN WILLIAMSON SILICON PHOTONICS
STANDING OUT IN THE SIPHO CROWD How do SiPho vendors differentiate their products? This is a question that Blum admits to having sometimes asked himself. In this context he considers that Intel has a unique capability of integrating III-V material, such as InP onto silicon at the wafer level, which gives the ability to have optical gain - for lasers and optical amplifiers - as part of its silicon photonics process. “We also manufacture on 300 mm wafers and are fully integrated, meaning we design and manufacture our photonic chips in-house,” he explains. “We also do a lot of in-house packaging, which is a key differentiator. For us a lot of differentiation comes not just from the design, but to a large extent from the manufacturing technology and scale.” According to Arabzadeh, SiPho product differentiation can come from factors such as cost of manufacture and packaging, and density and power consumption characteristics. To this end RANOVUS’ SiPho devices implement optical modulation on micro-ring resonator architecture, an arrangement designed to enable the achievement of very high densities and support high-speed modulation at data rates of up to 100 Gbps/lambda. The company also reckons to achieve industry benchmarks for lowest power consumption. COMING TO LIGHT There’s widespread optical industry consensus that there are various applications that should drive significant future volumes for SiPho deliveries. Blum believes that optical I/O, where photonics is connected to CPUs, GPUs, memory and accelerators, is undoubtedly one of them. “Imagine every server in a data centre and eventually every personal computer having embedded optical links that send Terabytes of data between compute and accelerator chips,” he proposes.
Besides optical I/O and co-packaged optics in the data centre Intel sees a lot of SiPho opportunities in sensing, such as for automotive LiDAR, biotech and consumer health. Arabzadeh also envisages a big SiPho future in medical sensing applications and autonomous vehicles. “SiPho is really good where you have very high density I/O connections,” he amplifies. “That is really where it shines. For low-capacity cases, other technologies could do a better job.” There’s also the expectation that there’s quite a bit more for SiPho to do in terms of speed and connectivity. Blum reports that Intel is working on a proof of concept for multi-Tbps chip-to-chip connections in the 2023 timeframe. “Photonics or optical I/O is just becoming another tile that can be packaged as part of larger assemblies using technologies such as EMIB or Foveros,” he asserts. EMIB (Embedded Multi-die Interconnect Bridge) is an approach to in-package, high density interconnect of heterogeneous chips. Foveros enables the building of processors with compute tiles stacked vertically, rather than side-by-side. What about SiPho being used to support connections between sections on the chips themselves? “To some extent we don’t really need photonics within a chip, since today’s advanced chips are really an assembly of multiple tiles with different functionalities, and moving forward so some these tiles can now be optical I/O tiles,” offers Blum.
fabric of hyperscale data centres to handle the unprecedented data volumes generated by innovations such as AI and ML, competing claims for pluggable optical modules and Co-Packaged Optics (CPO) are being made and scrutinised. At the risk of over-simplification, systems that use pluggable optics dissipate a lot of power sending signals back and forth to the CPU and switches and high- performance ICs on the PCBs. One of the advantages of the CPO approach of moving the optics closer to the ICs doing the brunt of the work is reduction of the power that’s being used. However, as Vang suggests, in the event of CPO failure you might need to replace a very expensive board rather than simply plug in a replacement module. Although pluggables may be a better established proposition, there have been some interesting CPO initiatives. One was the establishment by Microsoft and Facebook in March 2019 of the Co- Packaged Optics (CPO) Collaboration. The goal of the CPO Collaboration is the adoption of common design elements that will provide guidance for suppliers in the design and manufacturing of co- packaged optics. In February of last year, the Co-Packaged Optics Collaboration Joint Development Forum released a 3.2 Tbps Co-packaged Optical (CPO) Module Products Requirement (PRD). This PRD describes the requirements to build a 8 x 400 Gbps optical module targeted to increase network switch density and increase power efficiency. Bodies such as the Consortium for On-Board Optics (COBO) and the Optical Internetworking Forum (OIF) have also mounted programmes aimed at advancing the CPO cause. Meantime, both Intel and RANOVUS (the latter in a collaboration with IBM, TE Connectivity and Senko Advanced Components) are among the companies to have launched CPO products.
ALL ABOARD? Going forward, one technical and
operational strand of SiPho development with major ramifications for data centre deployments is now the subject of considerable industry discussion and investigation. With optical connections needing to penetrate deeper into the
Robert Blum, Senior Director Marketing and New Business, Silicon Photonics Division, Intel
Hamid Arabzadeh, Chairman, President, CEO, RANOVUS
Timothy Vang, VP, Semtech Signal Integrity Products Group
ISSUE 28 | Q1 2022
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