Influence of microstructural features on the synaptic behavior of polymer-based thin-film transistors Fu-Chiao Wu, Chun-Yu Chen, Wei-Yang Chou, Horng-Long Cheng National Cheng Kung University, Taiwan In this study, poly(3-hexylthiophene) (P3HT) as the active layer is used to fabricate ion-gel-gated thin-film transistors. Various methods are adopted to grow P3HT thin films, including spin-coating with thermal annealing (ST), spin-coating with solvent annealing (SS), and drop-casting with solvent annealing (DS). The DS and SS devices produce the largest and lowest drain current ( I D ), respectively. Compared with the ST and SS devices, the DS device has smaller subthreshold swing, indicating the existence of lower interfacial trap density. In the X-ray diffraction (XRD) patterns of various P3HT thin films, only the DS specimen has high-order diffraction peaks. Based on the information of XRD patterns, the DS specimen has the shortest d -spacing and the largest crystalline size, and the ST specimen has the longest d -spacing and the smallest crystalline size. These results indicate that the DS specimen possesses compact lamellar stacking and better crystalline structures, leading to a higher I D of the DS device. Although the microstructures of the SS specimen are better than those of the ST specimen, the ST device performs a larger I D than the SS device. For the SS device, during solvent annealing of P3HT, the underlying poly(methyl methacrylate) (PMMA, buffer layer) could permeate into P3HT and near the channel region. Those insulating PMMA can hinder charge transport, resulting in a lower I D of the SS device than the ST device. The synaptic behavior of different P3HT-based devices is investigated. The ST and DS devices produce increased excitatory postsynaptic current (EPSC)with increasing spike (gate bias) time, performing a synaptic potentiation behavior. The EPSC increment of the DS device is greater than that of the ST device, resulting from better microstructures and lower interfacial trap density of the DS device. Surprisingly, the SS device performs decreased EPSC with increasing spike time, showing a synaptic depression behavior. During the stimulation of a spike, holes could be captured by the PMMA near the channel region. Those captured holes can impede hole accumulation and hole transport. Hence, the increased spike time poses reduced EPSC of the SS device. During a paired-pulse stimulation, the EPSC of the ST and DS devices under the second pulse is higher than that under the first pulse, showing a paired-pulse facilitation (PPF) behavior. Compared with the ST device, the DS device has a larger PPF index because of the lower interfacial trap density and better microstructures. Interestingly, the SS device produces lower EPSC under the second pulse than the first pulse, performing a paired-pulse depression behavior. This behavior results from the suppressed hole transport and accumulation caused by the captured holes in PMMA. In addition, with an additional planar gate electrode, these P3HT-based devices can act as YES, OR, and XOR logic gates.
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© The Author(s), 2023
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