ADVANC ED S i P 2 0 2 0
Moore’s Law has driven the electronics industry for decades, but in recent years, it has decelerated and has started to plateau in terms of performance and economic benefit. The exponential cost of silicon scaling has created an inflection point for the industry. It is driving the development of More-Than-Moore to augment increased device and system performance. Heterogeneous integration through advanced packaging technology enables integration of system or sub-system modules with separate designs and different manufacturing process nodes within a single package. System-In Package (SiP) functionality is now driving the pace of advancement for more intelligence, more connectivity, higher bandwidth, higher performance, with lower latency and lower power per function at a more manageable cost.
Chiplets integration for HPC and AI/ML application As the industry enters the digital transformation and exascale computing era, massive compute with frequent access to data is required for high performance computing (HPC) applications. The increasing amount of data from all sectors is raising a problem of operational and storing cost of the data. The advent of artificial intelligence (AI) and machine learning (ML) has allowed large amounts of data to be processed and is driving an entirely new computing paradigm from edge computing to cloud to data center. Traditional IC design trends are to pack more transistors on a monolithic die or SoC at each process node, resulting in difficult chip scaling for integration of analog, logic and memory circuits. An alternative new solution of chiplets or die partitioning offers a compelling value proposition for yield improvement, IP reuse, performance and cost optimization, as well time to market reduction. Chiplet integration allows the integration of disparate technologies from multiple vendors to provide more flexible mix-and-match systems to accelerate performance and improve power efficiency without requiring deployment of these technologies across an entire SoC simultaneously. Chiplet solutions start with internal designs within a system integrator. However, as IP interface standards are developed, the commercialization of chiplets in the market will proliferate. As a result, chiplets will play a critical role for future HPC and AI/ML applications. Heterogeneous integration solutions in ASE As a leading semiconductor packaging, test and system service provider, ASE has heavily invested in chip level (SoC) package integration and the system level integration. ASE has developed cutting edge heterogeneous integration technologies addressing functional areas from silicon integration, power integration, optical integration to system integration (SIP) that form the backbone of many electronic devices.
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