IMAPS Advancing Microelectronics 2020 Issue 3 (Advanced SiP)

Advanced SiP Special Issue Vol. 47 No. 3

Advanced SiP

How AiP Technology Helps Enable 5G... Heterogeneous Integration Technologies...

WWW.IMAPS.ORG

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Features

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How AiP Technology Helps Enable 5G and More Vik Chaudhry, Sr. and Curtis Zwenger Heterogeneous Integration Technologies: Driving a new era for HPC and AI/ML Rich Rice and Lihong Cao

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On the Cover: HPC / AI Technology Drivers

A D V A N C I N G MICROELECTRONICS

C ONT ENTS

DEPARTMENTS From the IMAPS President Advancing Microelectronics Moves from Mailbox t o Inbox

MEMBER TOOLS

16 Chapter Contacts 20 Advertiser Hotline 20 Advancing Microelectronics 2020 Editorial Schedule 20 Who to Call at IMAPS HQ

UPDATES FROM IMAPS 3 JOBS Marketplace 5 IMAPSource 17 Individual Member Benefits 18 IMAPS Corporate and Premier Member Benefits 19 Premier Corporate Members

International Microelectronics Assembly & Packaging Society

INSIDE BACK COVER Calendar of Events

PO Box 110127 79 TW Alexander Dr. 4401 Building Suite 115 Research Triangle Park, NC 27709 USA Tel: +1-919-293-5000 E-Fax: +1-919-287-2339 See us on IMAPS’s Home Page: www.imaps.org

COMING NEXT ISSUE IMAPS 2020 Show Issue: Always On! Enabling a Connected World

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UP C OM I NG E V ENTS

Executive Council President Richard Rice ASE US, Inc. President-Elect Beth Keser Intel Corporation First Past President Ron Huemoeller Amkor Technology Vice President of Marketing Adrienne Gerard Finetech, Inc. Secretary Daniel Krueger Honeywell Treasurer Michael Gervais Geib Refining Corporation Directors

IMAPS Global Business Council (GBC) Live Webinar on Advanced Packaging Landscape in Post-COVID Economy Wednesday, August 19, 2020 | 12:00pm – 12:45pm EASTERN | MS Teams

ESTC 2020 8th Electronics System-Integration Technology Conference September 15-18, 2020 Vestfold, Norway

MicroTech 2020 Online, the IMAPS UK Annual Conference September 16, 2020 Online

IMAPS 2020 October 5-8, 2020 San Diego, California

Jon G Aday Illumina, Inc. Erica C Folk Northrop Grumman Mission Systems Prof Douglas C Hopkins, Ph.D. NCSU Packaging Research in Electronic Energy Systems (PREES) Dr. Ivan Ndip Fraunhofer Institute for Reliability and Microintegration IZM Ex-Officio (Executive Director) Michael O’Donoghue, IMAPS Publications Committee Editor , Journal of Microelectronics and Electronic Packaging John Pan, Cal Poly State University Managing Editor, Advancing Microelectronics Michael O’Donoghue

Visit www.imaps.org for links to all upcoming events including:

• full event descriptions • • abstract submissions • • exhibition information • • event updates •

Staff Director of Programs Brian Schieman

IMAPS JOBS MarketPlace

Your IMAPS membership provides you with the on-line JOBS MarketPlace. This is a proactive, valuable, complimentary member service for both job seekers and prospective employers. Take advantage of it to find open positions or fulfill staffing needs. IMAPS members can post unlimited job openings at no cost. Hiring managers can search for and view resumes of industry participants at no cost by using convenient sort criteria. Member job seekers can post resumes and/or search for current openings at no cost. Job seekers can make their search even easier by setting up a job alert so compatible openings (by industry, location, and job function criteria) will be e-mailed as they are posted.

Advancing Microelectronics (formerly Inside ISHM) is published six times a year and is a benefit of IMAPS membership. The annual subscription price is $95; $15 for a single copy. Copyright 2020 by IMAPS—International Microelectronics Assembly and Packaging Society. All rights reserved. Except as defined in 17 USC, Sec. 107, permission to republish any materials in this publication must be obtained from IMAPS, PO Box 110127, 79 TW Alexander Dr., 4401 Building Suite 115, Research Triangle Park, NC 27709. Telephone +1-919-293-5000.

Find out more information at to https://imaps.careerwebsite.com

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F ROM THE I MAP S PR E S I DENT

A Letter from Rich Rice, IMAPS President

Advancing Microelectronics Moves from Mailbox to Inbox

IMAPS is eager to reveal an exciting new facelift to our hallmark member magazine Advancing Microelectronics ! After years of mailbox delivery, the magazine has moved to a purely interactive digital format. The print publication of Advancing Microelectronics has already been complemented by publication in the ex - clusive IMAPSource digital archives for several years. This archived version of each issue will remain accessible to members and nonmembers alike, but the primary delivery of the magazine is shifting to a new, highly interactive platform with enhanced tools for authors, readers, and advertisers alike. You can expect: • Opportunities to share your voice and opinions via surveys and direct comments on our content • Expanded technical content no longer subject to the restraint of page limitations • More cost-effective marketing and product promotions for our corporate members • Interactive content such as videos, event registration links, and direct connections to advertisers • Enhanced electronic readability This is a timely and long overdue change for our signature publication, but the value of IMAPS membership is rooted in connections. We believe that the enhancements ushered in by this format will improve the quality of our members’ connections to the industry, only adding to the member experience. We look forward to hearing your impressions of the new Advancing Microelectronics .

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IMAPS members are pre-registered with IMAPSource and receive a profile confirmation email from Allen Press. This will help members gain unlimited download access to IMAPSource. Non-members and guests will need to click Register Now at IMAPSource.org. In 2020, free downloads will be subject to membership level below. Non-member downloads will be subject to a per-article charge.

2020 IMAPSource Membership Plans:

Number of downloads

Individual/Senior/Lifetime

100

Corporate

300

Premier Corporate/Academic Institutions

Unlimited*

Associate Corporate

Affiliate (International Chapters/Unemployed Members)

Student

Retired/Senior Retired/Corporate International

*Unlimited package allows multiple IP range and unlimited access

Contact IMAPS HQ today for more information about IMAPSource registration, member benefits, IP range setup for Premier Corporate and Academic Institution members and more!

F EATUR E ART I C L E

ow AiP Technology Helps Enable 5G and More

By Vik Chaudhry, Sr. Director, Product Marketing and Business Development and Curtis Zwenger, VP, Advanced Package & Technology Integration, Amkor Technology, Inc.

For 5G smartphones and other millimeter wave (mmWave) applications, antenna integration, either through antenna in package (AiP) or antenna on package (AoP) technologies, simplifies the challenges associated with designing products that operate at these high frequencies. A variety of AiP/AoP design methodologies provide the required form, fit and function for these applications and can include more than one antenna or an antenna array. Today’s AiP/AoP technologies can be implemented through standard as well as custom System in Package (SiP) modules to achieve a complete radio frequency (RF) front-end (RFFE) subsystem. Projected Growth for 5G, mmWave and RFFE Modules In mmWave applications, signal loss becomes critical and the design challenges increase in complexity. In addition to emerging 5G smartphones, other applications that operate at very high frequencies and demand a small size include wearables, small cells, security cameras, radar units in autonomous vehicles and numerous Internet of Things (IoT) wireless nodes. By 2023 over 1 billion mmWave units will be produced annually according to Gartner market research. With AiP technology, the antenna is no longer a separate component within the wireless device but is integrated in a SiP with RF switches, filters and amplifiers. According to consulting firm Yole Développement, the total RFFE module SiP market is projected to reach US $5.3 billion by 2023, representing an 11.3% compound annual growth rate (CAGR). AiP/AoP at Amkor Instead of separate RF system on chip (SoC), baseband (BB) SoC, surface mount technology (SMT) matching circuits and a discrete antenna, today’s fully integrated RF front-end module is completely achieved with AiP technology in SiP. In addition to reduced size required for handheld and other small mmWave devices, AiP/AoP provides improved signal integrity with reduced signal attenuation and addresses the range and propagation challenges that occur at higher frequencies. As a leading outsourced semiconductor assembly and test (OSAT) supplier, Amkor has pioneered the packaging technologies required for RFEE subsystems.

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Design Services & Design/Production Capabilities for AiP/AoP For AiP/AoP technologies, Amkor has developed an extensive toolset to maximize circuit density and ad - dress the sophisticated packaging formats required for high-volume production of 5G and any mmWave de- sign. In addition to an advanced multi-die integration toolbox and RF SiP design and simulation know-how, other capabilities include: • Extensive fcCSP, WLCSP, LDFO and HDFO portfolios for multi-die designs

Implementing AiP/AoP Technologies Depending on the frequency range, different platforms are used for both the antenna and the IC package. In addition to AiP, the integrated antenna can be mounted on the package (AoP), or on a substrate (AoS), or in a SiP mmWave antenna module and the AiP approach itself can vary from package to package. For applications below 6 GHz, a Flip Chip Ball Grid Array (FCBGA) or double-sided ball grid array (DSBGA) are two possibilities. For applications in the 28 GHz to 39 GHz range, the antenna could be a SiP module antenna or a Flip Chip Chip Scale Package (fcCSP) with package on package (PoP) antenna. Applications in the 60 to 77 GHz range benefit from a wafer level or Low- Density Fan-Out (LDFO) package to the most advanced High-Density Fan-Out (HDFO) packaging. RF shielding techniques include dual-side mold, conformal shield, compartment shield using laser trench and paste filling technology, partial molding, selective conformal shielding and hybrid SiP designs. These techniques implement a variety of materials to conductive lids as well as cored, coreless and low coefficient of thermal expansion (CTE) and conformal shielding materials. Packaging technologies for AiP/AoP include: • Body sizes up to 23.0 mm x 6.0 mm with several smaller options • Up to 14 substrate layers • Thin-film redistribution layer (RDL) and dielectrics for 77 GHz and higher applications With Amkor AiP/AoP technologies, system designers get: • A smaller footprint-phased antenna array design to minimize space • Reduced signal attenuation for mmWave products • Lower power consumption • Improved range for devices • A design proven and qualified by the supplier In fact, Amkor’s AiP/AoP packaging technologies have achieved over 60 GHz operation.

• An established and reliable supply chain • Global assembly scale and system test investments • RD design & measurement lab

Initiating an AiP/AoP Design Amkor offers many options to incorporate AiP/AoP in a variety of packages or SiP and the high-volume production capacity to support the design of the next generation mmWave products. To integrate Amkor’s market leading 5G and mmWave packaging technology in a next generation application, system designers simply need to contact Amkor and discuss their system requirements.

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eterogeneous Integration Technologies: Driving a new era for HPC and AI/ML

Co-Authors: Rich Rice, Sr. Vice President, Marketing & Technical Promotion, ASE Group Lihong Cao, Director, Engineering, Marketing & Technical Promotion, ASE Group

The digital transformation has encompassed multiple sectors including consumer, industrial, automotive and healthcare. Holistic enterprise infrastructure from cloud to data centers coupled with intelligent edge computing utilizing 5G and AI will drive semiconductor industry growth in coming years. High technology companies have taken the 7/10 top spots in the top global companies by market capitalization to lead the new digital transformation era in 2019 compared to only 1/10 tech company in 2006. Certainly, this is a new era where digitization will permeate almost all over the world, where essentially data is the new oil!

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Moore’s Law has driven the electronics industry for decades, but in recent years, it has decelerated and has started to plateau in terms of performance and economic benefit. The exponential cost of silicon scaling has created an inflection point for the industry. It is driving the development of More-Than-Moore to augment increased device and system performance. Heterogeneous integration through advanced packaging technology enables integration of system or sub-system modules with separate designs and different manufacturing process nodes within a single package. System-In Package (SiP) functionality is now driving the pace of advancement for more intelligence, more connectivity, higher bandwidth, higher performance, with lower latency and lower power per function at a more manageable cost.

Chiplets integration for HPC and AI/ML application As the industry enters the digital transformation and exascale computing era, massive compute with frequent access to data is required for high performance computing (HPC) applications. The increasing amount of data from all sectors is raising a problem of operational and storing cost of the data. The advent of artificial intelligence (AI) and machine learning (ML) has allowed large amounts of data to be processed and is driving an entirely new computing paradigm from edge computing to cloud to data center. Traditional IC design trends are to pack more transistors on a monolithic die or SoC at each process node, resulting in difficult chip scaling for integration of analog, logic and memory circuits. An alternative new solution of chiplets or die partitioning offers a compelling value proposition for yield improvement, IP reuse, performance and cost optimization, as well time to market reduction. Chiplet integration allows the integration of disparate technologies from multiple vendors to provide more flexible mix-and-match systems to accelerate performance and improve power efficiency without requiring deployment of these technologies across an entire SoC simultaneously. Chiplet solutions start with internal designs within a system integrator. However, as IP interface standards are developed, the commercialization of chiplets in the market will proliferate. As a result, chiplets will play a critical role for future HPC and AI/ML applications. Heterogeneous integration solutions in ASE As a leading semiconductor packaging, test and system service provider, ASE has heavily invested in chip level (SoC) package integration and the system level integration. ASE has developed cutting edge heterogeneous integration technologies addressing functional areas from silicon integration, power integration, optical integration to system integration (SIP) that form the backbone of many electronic devices.

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Si integration solutions for chiplets ASE has developed and offers a wide portfolio of Si level integration technology solutions, from low density to high density chiplets integration including FCMCM (Flip-chip multi-chip-module), FOCoS (Fanout chip on substrate) and 3D IC. The advanced FOCoS technology can provide short die to die connection and high interconnections (10,000’s) with RDL (redistribution layer) small line/space (L/S) 2/2um up to 4 layers for Chip First and Chip Last packaging processes. It also produces a lower cost solution with improved electrical performance compared to 2.5D Si interposer solution due to the elimination of Si TSV process and reduced insertion loss. ASE is evolving this ad - vanced packaging platform to meet application demands for HPC and AI/ML applications.

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Optical As massive amounts of data are processed, it must all be transmitted to and through large data centers. Transmission through copper interconnect uses massive amounts of power, which is a big and growing problem for data center operators. Deployment of silicon photonics for traffic inside the data center, to the server boards, and eventually directly to the network switch components will have a dramatic effect on overall power reduction, and this is a big driver for implementing optical interconnect. In addition, switching bandwidth of 50Tbps will be enabled, which massively increases data throughput.

Power Delivery Power consumption for high performance processors, FPGAs, and ASICs continues to increase as overall device switching speeds continue to rise. As transistors shrink in finer lithography nodes, lower operating voltages required. With the number of cores increasing, it is imperative to have ample power supplied to the chip to avoid voltage droop, to ensure functionality between the processor, memory and other functional elements of the packaged sub - system, all which optimize the performance. New approaches to power deliver are being developed in the areas of wafer level solutions (trench capacitors), package level solutions (embedded capacitive and inductive elements in the substrate), and system level solutions (integrated power modules). All of these approaches are viable and bring the necessary current at specified voltages close to the processor, thus increasing the power deliver efficiency and reducing overall power required. These power delivery approaches also reduce the amount of power circuitry on the Looking into the future, all of these key developments in packaging that create higher performance systems that utilize less power will be deployed. The end result will be to produce system performance that continues the trend of Moore’s Law, albeit in a different way than with previous total reliance on semiconductor chip lithography and SOC integration. At ASE, we strive to work closely with our customers to create the necessary IC packaging and system level solutions to make this a reality. system board, reducing board space and cost. HPC/AI Compute Platform of the Future

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This is an exciting time for the IC packaging industry. Innovation in these critical areas marches on, with the ulti- mate goal of enabling new solutions and applications that make our world smarter, more efficient, and, and overall better place to live, work and play.

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Innovative IC, SiP, and MEMS packaging portfolio to serve dynamic mobility, IoT, high performance computing, and automotive markets. PoP • Flip Chip • SiP • WLP • Fanout • FOCoS 2.5D • TSV • Flex • AoP • AiP • Shielding Wire Bond • Embedded • Substrate • Co-Design

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VIRTUAL EXHIBITOR PLANNING IMAPS 2020 offers exhibitors the choice of three virtual exhibit environments.

Download Application

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Final deadline to apply for exhibit space is September 4th.

Click for details and 3D tour

Exhibitor Package Inclusions All IMAPS 2020 virtual exhibit package include:

• Development and presentation of an interactive virtual exhibit environment featuring 2-6 touchpoints, exhibitor description and website link • Searchable listing on sponsor and exhibitor page • Bonus link to external site of exhibitor choice during Swag Day • One or two full symposium registrations • Unlimited additional full registrations for $300 per person • Pre- and post-show registration lists in PDF format • Touchpoint click/hover count reports and analytics • Hands-on support during the virtual exhibit development process

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CHAPTER NAME

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Leadership recruitment in progress

Interested? Contact Brianne Lamm blamm@imaps.org

Carolinas

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MEMB E R SH I P

Premier Corporate Members IMAPS has introduced a new level of support for corporate members. These companies have decided to participate in our Society at the Premier Corporate Member level. We are extremely grateful for their dedication to the furtherance of our educational opportunities and technological goals.

Semiconductor Technologies

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ASE Group

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908-429-3578

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Master Bond

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201-343-8983

info@masterbond.com

www.masterbond.com 12

Mini-Systems, Inc.

Craig Tourgee

back cover

508-695-0203 ctourgee@mini-systemsinc.com www.mini-systemsinc.com

NAMICS Technologies, Inc.

Ken Araujo

774-328-9635 araujo@namics-usa.com

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Advancing Microelectronics Editorial Schedule **MAX OF 3 PAPERS PER ISSUE**

Issue

Theme

Jul/Aug 2020

IMAPS 2020 Show Issue

Sep/Oct 2020

Advanced Materials and Additive Manufacturing

Nov/Dec 2020

Chip Package Interaction (CPI)

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CAL ENDAR O F E V ENTS

2020 AUGUST

start

end

8-19-20 8-19-20 IMAPS Global Business Council (GBC) Live Webinar on Advanced Packaging Landscape in Post-COVID Economy

12:00pm – 12:45pm EASTERN | MS Teams imaps.org/gbc_live_webinar_19aug20.php

9-15-20 9-18-20 8th Electronics System-Integration Technology Conference Vestfold, Norway 9-16-20 9-16-20 MicroTech 2020 Online, the IMAPS UK Annual Conference Online

SEPTEMBER

www.imaps.org.uk/events/microtech-2020-online-advanced-packaging/

10-5-20 10-8-20 IMAPS 2020

OCTOBER

San Diego, California

Visit www.imaps.org for links to all upcoming events including:

• full event descriptions • abstract submissions • exhibition information • event updates

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